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RollPlace: Improving Macro Placement via Monte Carlo Rollout Search
Qi Zhou, Guojun Liu, Guangzhi Qi, Ming Lu, Jiechu Liu, Zhongli Liu, Jianqun Yang, Xingji Li
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Abstract
Abstract:The application of Reinforcement Learning (RL) in Electronic Design Automation (EDA), particularly for chip placement, has attracted considerable attention in recent years. While existing machine learning (ML)-based approaches have achieved notable progress, they predominantly focus on generating optimal layouts in a single attempt, often producing solutions that require subsequent refinement. To address this limitation, we propose RollPlace, a novel and generalized macro placement framework. RollPlace adopts a two-stage optimization strategy: generating initial placement solutions via machine learning methods or heuristic-based strategies, and refining these layouts efficiently by adjusting specific macros derived from the initial stage. This strategy circumvents the sequential generation constraints inherent in traditional RL-based placement methods. Furthermore, RollPlace seamlessly integrates Monte Carlo Tree Search (MCTS) to balance exploration and exploitation, and employs a rollout mechanism for efficient local search. Extensive experiments on the ISPD 2005 benchmark demonstrate that RollPlace outperforms state-of-the-art methods. Additionally, end-to-end experimental results based on OpenROAD across 19 benchmarks show that RollPlace excels in multiple metrics. The proposed framework offers a robust and scalable solution for addressing the growing complexity of modern chip design challenges.
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- Source: https://arxiv.org/abs/2610.06316v1
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RollPlace: Improving Macro Placement via Monte Carlo Rollout SearchThanks: This work was supported in part by the National Natural Science Foundation of China (61976071), the Natural Science Foundation of Heilongjiang Province of China (LH2020F012), and the National Key Research and Development Plan Task of China (2021YFF0307903). (Corresponding author: Guojun Liu.)Thanks: Qi Zhou, Guojun Liu, Guangzhi Qi, Ming Lu, and Jiechu Liu are with the Faculty of Computing, Harbin Institute of Technology, Harbin, 150001, China. (e-mail: hitliu@hit.edu.cn).Thanks: Zhongli Liu, Jianqun Yang, and Xingji Li are with the School of Materials Science and Engineering, Harbin Institute of Technology, Harbin, 150001, China. Qi Zhou Guojun Liu Guangzhi Qi Ming Lu Jiechu Liu Zhongli Liu Jianqun Yang Affiliation: and Xingji Li, Abstract The application of Reinforcement Learning (RL) in Electronic Design Automation (EDA), particularly for chip placement, has attracted considerable attention in recent years. While existing machine learning (ML)-based approaches have achieved notable progress, they predominantly focus on generating optimal layouts in a single attempt, often producing solutions that require subsequent refinement. To address this limitation, we propose RollPlace, a novel and generalized macro placement framework. RollPlace adopts a two-stage optimization strategy: generating initial placement solutions via machine learning methods or heuristic-based strategies, and refining these layouts efficiently by adjusting specific macros derived from the initial stage. This strategy circumvents the sequential generation constraints inherent in traditional RL-based placement methods. Furthermore, RollPlace seamlessly integrates Monte Carlo Tree Search (MCTS) to balance exploration and exploitation, and employs a rollout mechanism for efficient local search. Extensive experiments on the ISPD 2005 benchmark demonstrate that RollPlace outperforms state-of-the-art methods. Additionally, end-to-end experimental results based on OpenROAD across 19 benchmarks show that RollPlace excels in multiple metrics. The proposed framework offers a robust and scalable solution for addressing the growing complexity of modern chip design challenges. Index Terms: Macro Placement, Chip Design, MCTS, Machine Learning I Introduction MACRO placement, a critical stage in chip design, involves positioning macros of varying dimensions on the chip canvas while satisfying stringent design constraints. The quality of macro placement profoundly impacts the performance metrics of the integrated circuits (ICs), including timing, power consumption, area utilization and so on. However, evaluating the quality of a macro layout typically necessitates the complete placement of all macros, often requiring designers to iteratively refine multiple layouts to achieve an optimal configuration. This challenge is exacerbated in modern very-large-scale integration (VLSI) circuits, where the presence of hundreds of macros and tens of thousands of standard cells compounds the complexity of the design. As semiconductor technology advances, this scale is expected to grow further, intensifying demands for scalable placement solutions. Consequently, the ability to rapidly generate efficient and high-quality layouts has become a critical challenge in chip design, driving the need for innovative solutions to address the escalating complexity of modern ICs. Fig. 1: The general process of placing macros one by one in reinforcement learning. In each state sts_t, the position of the t-th macro is determined according to the decision ata_t given by the agent, and the environment gives the reward value rtr_t. In recent years, numerous efforts have been made [1, 2, 3] to apply ML techniques to address the placement problem in EDA. Some of these endeavors have yielded remarkable results, significantly propelling the development and advancement of ML methodologies in the field of chip design. A common framework adopted by these methods is to model the chip placement task as a Markov Decision Process (MDP) [1]. As shown in Fig. 1, at each step, a macro is positioned on the canvas based on the agent’s decision. Upon completing the placement of all macros, relevant evaluation metrics, such as wirelength and congestion, are computed based on the macros’ positions and the netlist to assess the quality of the placement solution. In the aforementioned framework, placing the t-th macro inherently depends on the decision made at step t−1t\!-\!1, allowing the macro placement results to be represented as a sequence. However, a critical limitation of these approaches lies in their sequential nature: these ML-based approaches often generate the positions of all macros in a single forward pass without additional modifications or adjustments. This sequential dependency introduces a significant challenge: the position of a macro with a smaller index in the resulting sequence frequently influences the position of macros with larger indices. Generally, a benchmark usually contains at least hundreds of macros, and generating such a long sequence in a single attempt inevitably amplifies and accumulates deviations, ultimately degrading the overall quality of the layout. Recent attempts have been made to integrate ML-based methods with heuristic techniques to address the instability inherent in sequential macro placement solutions. Shi et al. [4] employed an evolutionary algorithm, named WireMask-EA, to fine-tune the placement results generated by MaskPlace [2]. Nevertheless, WireMask-EA exhibits inherent limitations in optimizing macro placement. Specifically, the algorithm focuses exclusively on refining the single optimal solution provided by MaskPlace, ignoring other potentially viable candidate solutions. This design inherently restricts the optimization space, potentially leading to suboptimal performance. In particular, when the initial placement from MaskPlace produces densely packed macros, the limited flexibility for subsequent adjustments severely constrains the algorithm’s ability to improve the layout. Another approach, EfficientPlace [5], combines RL techniques with tree search to enhance macro placement. This method simultaneously explores better sequences while optimizing the layout strategy through RL. However, EfficientPlace adopts a fixed macro ordering strategy, which overlooks the critical influence of macro sequence on placement quality. This rigidity can lead to suboptimal outcomes, as unsatisfactory search results in the early stages of the process may propagate errors and adversely affect the subsequent layout strategy. Consequently, the pre-determined ordering of macros limits the algorithm’s ability to adapt and explore alternative configurations that might yield superior results. Fig. 2: RollPlace framework. In the first stage, multiple initial layouts are generated and a search tree is constructed using ML methods or others. In the second stage, candidate solutions are refined via a Monte Carlo rollout search, including selection, order exchange, simulation, rollout and update. The right black rectangle illustrates the process of simulation and rollout. In this paper, we propose RollPlace, a novel macro placement framework that synergistically integrates ML techniques and heuristic functions, as illustrated in Fig. 2. RollPlace initially employs ML or heuristic layout strategies to generate initialization sequences. This capability enables the efficient generation of candidate sequences for chips that have not been previously encountered, significantly enhancing the framework’s generalization ability. Subsequently, these initialization sequences are utilized to construct a search tree, which is iteratively refined using MCTS and rollout strategies [6, 7, 8]. This iterative refinement process allows RollPlace to explore and optimize the solution space effectively, overcoming the instability issues inherent in traditional one-pass ML-based methods. The key contributions of this work are summarized as follows: • We identify and address a critical limitation in existing ML-based macro placement methods: the instability of one-time sequence generation. To mitigate this issue, we propose a novel framework that combines ML with heuristic algorithms through the construction of a Monte Carlo search tree. • To overcome the challenge of limited or non-existent position adjustment flexibility for macros with higher index values, we introduce a swap-based rollout algorithm. This component seamlessly integrates with the Monte Carlo rollout search, enabling dynamic adjustments to macro positions and significantly improving placement quality. • Extensive experimental evaluations demonstrate that RollPlace consistently outperforms state-of-the-art methods across multiple benchmarks in macro placement tasks. Furthermore, the framework exhibits robust performance in mixed-size placement tasks, highlighting its versatility and practical applicability in real-world chip design scenarios. The end-to-end evaluation based on OpenROAD [9] demonstrates that our algorithm retains significant advantages throughout the complete chip design workflow. I Related Work I-A Optimization-based Methods The macro placement problem, fundamentally a combinatorial optimization challenge, can be addressed through various optimization algorithms. At present, optimization-based placement methods can be broadly categorized into three main types: partitioning-based, simulation annealing-based, and analytical-based approaches. Partition-based Methods. Partition-based methods [10, 11] adopt the divide-and-conquer strategy by initially dividing the entire circuit into smaller sub-circuits. Specifically, after partitioning, the placement problem for each sub-circuit is addressed independently within its designated sub-region on the chip. Subsequently, these sub-regions are adjusted to suitable positions on the chip. However, a significant challenge may arise when dealing with circuits exhibiting diverse topological structures, as partitioning them into relatively independent sub-circuits can be very challenging. Simulation Annealing-based Methods. For another perspective, macro placement can be formulated as a Black-Box Optimization (BBO) problem. Simulated Annealing (SA) methods [12, 13, 14], also referred to as hill-climbing methods, are widely used iterative heuristic algorithms for solving such BBO problems. These methods generate new solutions through genotype perturbation and phenotype evaluation. Furthermore, various solution representation techniques have been proposed, including sequence pair (SP) [15] , B*-tree [16], and corner block list (CBL) [17]. These genotype representations are subsequently translated into specific macro placement configurations for evaluation. Recently, the WireMask-BBO framework [4] introduced the concept of wire mask [2], which enhances the efficiency of BBO algorithms in the genotype space and facilitates integration with multiple BBO algorithms. To accurately capture the structural characteristics and dataflow of Register Transfer Level (RTL) designs produced by automatic RTL generators, Kahng et al. proposed a novel macro placement tool named RTL-MP [18]. RTL-MP clusters RTL netlists to reduce problem scale while preserving dataflow and functionality, and places the clusters using simulated annealing. To further enhance the capability of handling large-scale and complex IP block macro placements, Kahng et al. subsequently proposed Hier-RTLMP [19], a hierarchical macro placement framework that leverages the intrinsic hierarchy and dataflow characteristics of RTL designs for multi-scale hierarchical optimization. Notably, Hier-RTLMP has been integrated into the open-source RTL-to-GDSII toolchain OpenROAD [9], thereby strengthening OpenROAD’s capacity to deliver reproducible and scalable PPA evaluation for academic research. Analytical-based Methods. Analytical-based methods relax the placement task to a mathematical programming problem. These approaches transform the optimization objectives into analytical functions of module coordinates. Based on the nature of these analytical functions, analytical-based methods can be broadly classified into two categories: quadratic methods [20, 21, 22, 23, 24, 25, 26] and nonlinear (non-quadratic) methods [27, 28, 29, 30, 31, 32]. Quadratic methods are computationally efficient but often produce lower-quality results. In contrast, nonlinear optimization methods provide a more accurate approximation of the cost function, albeit at the expense of significantly higher computational complexity. Recently, DREAMPlace [33, 30], a high-performance analytical-based method, has been developed. Built upon the foundations of NTUplace3 [27], ePlace [28] and RePlace [29], DREAMPlace leverages the PyTorch deep learning toolkit to reformulate the analytical placement problem as a neural network training task, thereby significantly accelerating the placement process. Further extending the capabilities of DREAMPlace, Agnesina et al. [34] proposed an enhanced framework that incorporates multi-objective Bayesian optimization for macro placement, thereby improving the potential achievable power-performance-area (PPA) by tuning the parameters. Liu et al. [35] also developed an extremely fast and extensible GPU-accelerated placer called Xplace, which considers operator-level optimization factors. Xplace achieves a 2x speedup compared to DREAMPlace while obtaining higher-quality solutions. I-B Learning-based Methods The escalating complexity of modern chip designs, driven by the increasing number of macros, has significantly challenged traditional placement methods. In response to these challenges, RL-based approaches have emerged as a promising solution for macro placement, demonstrating remarkable potential in addressing the limitations of conventional techniques. The foundation of RL-based macro placement was established by Google’s pioneering work [36], which formulated the macro placement task as a Markov Decision Process. This approach focused on minimizing the Half-Perimeter Wirelength (HPWL) but faced the challenge of sparse reward signals, which hindered efficient learning. To address this limitation, MaskPlace [2] introduced a novel framework incorporating three specialized masks: view mask, position mask, and wire mask. The wire mask, in particular, enabled the calculation of immediate rewards for macro positions, effectively mitigating the sparse reward problem and enhancing the learning efficiency of RL agents. Further advancements include PRNet [37], which incorporates the overlap area of macros into its reward function as a penalty term. This approach effectively reduces the potential issue of overlapping placement that violates design constraints. In response to the problem that RL-based methods take a long time to train in unseen circuits, Lai et al. [3] proposed a new transferable placement method based on transformer architecture [38, 39, 40], named ChiPFormer. Their approach leveraged offline training with collected placement data and online fine-tuning for unseen chip circuits [41], effectively reducing the runtime while maintaining high placement quality. Despite these advancements, existing RL-based macro placement algorithms often suffer from inefficiency, typically requiring extensive offline expert data or substantial online training. To overcome this limitation, Geng et al. [5] proposed EfficientPlace, a sample-efficient framework that combines local policy learning with global tree search algorithms. This innovative approach enables iterative optimization of placements, achieving superior quality with reduced runtime compared to traditional RL-based methods. I Preliminary Modern chip design is a highly structured process comprising multiple interdependent stages, including System Specification, Architecture Design, RTL Design, Logic Synthesis, Physical Design, and others [42]. Among these, chip placement constitutes a critical phase within Physical Design, where the primary objective is to optimize the spatial arrangement of movable macros and standard cells on the chip layout. This optimization must satisfy a complex set of constraints, including but not limited to overlap avoidance, congestion management, and density distribution control, while simultaneously striving to minimize critical design metrics such as wirelength and power consumption. Contemporary macro placement benchmarks, which serve as the foundation for evaluating placement algorithms, typically feature hundreds of macros and tens of thousands of standard cells. It is noteworthy that these numbers are substantially higher in state-of-the-art industrial chip designs, further exacerbating the computational complexity of the placement problem. Since existing ML-based methods place cells sequentially, the resulting design space becomes excessively large, making it computationally intractable for neural networks to handle effectively. Consequently, most ML-based approaches focus solely on determining the optimal placement of macros on the layout, while the placement of standard cells is typically resolved using alternative methods, such as the force-directed approach [36] or advanced tools like DREAMPlace [30]. I-A Problem Formulation Macro placement. The input to macro placement can be expressed as a hypergraph H=(V,E)H=(V,E), where V represents the set of nodes (macros) and E represents the set of edges (netlist), which describes the connection relationships between nodes and the offset of pins. The macro placement solution can be expressed as a sequence (xi,yi)i=1N\(x_i,y_i)\_i=1^N that describes the locations of the macros, where (xi,yi)(x_i,y_i) represents the two-dimensional coordinates of the macro i on the physical layout. N is the total number of macros. To simplify the problem, this paper focuses on minimizing HPWL while disregarding overlap constraints, as presented in the following equation: min HPWL(H) (H) (1) s.t. s.t. Overlap (,,,)=0 Overlap ( x, y, w, h)=0 where x and y denote the positions of macros, w and h represent the width and height of macros. HPWL. Following established practices in physical design optimization, we employ HPWL as a computationally efficient approximation for estimating interconnect length, as the exact wirelength can only be determined after global routing completion. HPWL serves as a fundamental metric for wirelength estimation due to its computational efficiency and strong correlation with actual routing length [43, 44]. The HPWL for a given net is calculated as the sum of the horizontal and vertical spans of its minimum bounding box, encompassing all connected pins. Given a specific net eie_i, the HPWL is mathematically defined as: HPWLi _i =(maxb∈eixb−minb∈eixb) = ( _b∈ e_i \x_b \- _b∈ e_i \x_b \ ) (2) +(maxb∈eiyb−minb∈eiyb) + ( _b∈ e_i \y_b \- _b∈ e_i \y_b \ ) where xbx_b and yby_b represent the two-dimensional coordinates of pin locations, determined by the placement of macros and the relative offsets of pins within net eie_i. The total HPWL for the complete hypergraph H is then computed as the summation of individual net HPWL across all nets in the design, as expressed in (3): HPWL(H)=∑ei∈EHPWLiHPWL(H)= _e_i∈ EHPWL_i (3) I-B Notations We define the problem of macro placement H=(V,E)H=(V,E) with N macros, where node i∈1,⋯,Ni∈\1,·s,N\ is represented by mi∈Vm_i∈ V and net i is denoted by ei∈Ee_i∈ E. For macro placement, H is a hypergraph which means two nodes may be directly connected by multiple different lines. A solution is defined as =π1,⋯,πN π=\ _1,·s, _N\, where πi=(xi,yi) _i=(x_i,y_i) is the coordinate of node mim_i in physical layout. Similar to the previous work, the entire canvas can be divided evenly into M×M× M grids (where M represents the number of divisions along each edge of the canvas, and is a positive integer), with each grid representing a coordinate position. Therefore, all coordinate values of the solution are selected from discrete M×M× M grids. We place macros on the canvas step by step, which can be represented as a sequential decision model. For notation consistency, we define the empty sequence π1:0=∅ _1:0= (i.e., no previous decisions) when t=1t=1. In our framework, the heuristic function can generate a stochastic policy p(|H)p( π|H) to determine a solution π given a problem instance H and previous solutions π1:t−1 _1:t-1: p(|H)=∏t=1Np(πt|H,π1:t−1).p( π|H)= _t=1^Np ( _t|H, _1:t-1 ). (4) In the context of macro placement, once the position of the node preceding step i is determined, their order can be arbitrarily rearranged without affecting the state of the current node mim_i or altering the placement policy p for the remaining nodes. As a result, the order of the preceding nodes is irrelevant in our framework, whereas their coordinates play a critical role. IV Method IV-A Motivation One-Time Generation. Modern ML-based macro placement methods are predominantly implemented with RL algorithms, where the placement problem is formulated as a Markov Decision Process. In RL-based framework, macros are placed sequentially on the canvas, with each placement decision influencing subsequent states and actions. Specifically, the position of each newly placed macro becomes part of the state space that determines the placement of subsequent macros. This sequential dependency creates a deterministic generation process where the final placement configuration is fully determined once the last macro is placed. We characterize this approach as one-time generation, which inherently limits the flexibility to refine or adjust placements after the initial generation process. This one-time generation paradigm stands in stark contrast to traditional manual placement methodologies. In manual macro placement, designers maintain complete flexibility to select and reposition any macro at any suitable position on the canvas, without adhering to a predefined order. This iterative refinement capability allows for continuous optimization and adjustment of placement configurations, enabling designers to achieve superior placement quality. Consequently, it is essential to fine-tune the results of one-time generation to achieve better placement outcomes. Fixed Macro Ordering. Another limitation of the sequential decision-generation approach is that macros for a given benchmark are typically placed in a fixed order, which can lead to the issue of error accumulation. If an early macro placement is suboptimal, subsequent decisions become constrained by this initial error, potentially propagating and amplifying the degradation of placement quality. Consequently, in a step by step generation framework, dynamically adjusting the macro placement order can effectively mitigate the error accumulation problem. IV-B Framework To address these challenges, we propose a novel framework that integrates ML with Monte Carlo tree search to resolve the previous issues. Additionally, the framework employs heuristic search and a non-deterministic macro ordering strategy to overcome the limitations associated with fixed macro placement sequences, as illustrated in Fig. 2. First, a set of initial solutions is generated with RL approach or heuristic-based strategies, to construct a search tree in which each solution represents a distinct branch. Subsequently, we select an appropriate sequence (xi,yi)i=1N\(x_i,y_i)\_i=1^N as a candidate solution can π_can from the tree and perform a local search on can π_can in a swappable order. Once a new solution new π_new is generated, the positional order is adjusted to align with can π_can. Finally, the HPWL [43, 45] of new π_new is computed, and the search tree is updated accordingly. This iterative cycle—selection, order exchange, simulation, rollout, and update—continues until reaching a predefined number of iterations. The proposed algorithm is structured into two distinct stages. In the first stage, a set of initial solutions ii=1P\ π_i\_i=1^P is generated, and a search tree is constructed based on these solutions. In the second stage, the one-time generated solutions are further refined via a Monte Carlo rollout search. The flow of the second stage is summarized in Algorithm 1. Code is publicly available at https://github.com/smartbird66/RollPlace. IV-C Initialize Placement The transferable ML-based methods or fast placers are recommended to initialize placement in our framework. These approaches significantly reduce the time required for chip placement. Taking ChiPFormer [3] as an example, unlike other RL placement methods that rely on convolutional neural networks (CNNs), a sequential decision-making module fθf_θ with parameter θ was trained on a chip placement dataset, followed by an offline fine-tuning for the target chip. For different target chips, only a simple fine-tune of the pre-trained model is required, eliminating the need to train a neural network from scratch. IV-D Monte Carlo Rollout Search Our RollPlace framework is depicted in Fig. 2. In the search tree, each solution is represented as a fixed sequence πii=1N\ _i\_i=1^N. Since fixed-order macro placement can degrade placement quality, we propose a rollout strategy to perform randomized local optimization. This strategy randomly swaps the placement order of selected macros and employs a stochastic approach to locally optimize the sequence, thereby addressing the fixed order limitation inherent in existing methods. Our method further integrates a heuristic search strategy based on position mask and wire mask, as introduced in [2]. Specific details of the strategy will be elaborated in section IV-E. The flexibility to modify the macro placement order stems from the following property of macro sequences: once all macros are placed under constraints, the position of any one or more macros can be adjusted, provided that the new positions still satisfy the constraints. Such adjustments result in a valid solution. For instance, as illustrated in Fig. 3, consider a solution π where all macros satisfy the constraint overlap=0overlap=0. A subsequence sub π_sub is sampled from π, and both sub π_sub and −sub π- π_sub satisfy the constraint. By fixing −sub π- π_sub and adjusting sub π_sub according to the policy p while maintaining constraint satisfaction, a new sequence −sub+sub′ π- π_sub+ π_sub is obtained. This new sequence remains a valid solution as it still satisfies the constraint. This process is equivalent to first placing the macros of −sub π- π_sub in their existing positions, and then placing the macros of sub π_sub. Consequently, randomly swapping macros based on this property does not affect the final placement outcome. Fig. 3: Macro adjustment. (a) π is the original solution, (b) sub π_sub is the subsequence which are going to be adjust, and (c) −sub π- π_sub keeps the original position. (a) π (b) sub π_sub (c) −sub π- π_sub The following section provides a detailed description of the Monte Carlo rollout search. Selection. In the selection phase, identifying an appropriate candidate solution can π_can is critical for the effective execution of subsequent search operations. Starting from the root, successive child nodes are selected until a leaf node is reached. The root node is a virtual node, regarded as layer 00, while the remaining nodes are organized into layers 11 through N from top to bottom. Each node in layer i corresponds to a policy πi _i. A complete solution is represented by a full path from layer 11 to layer N. To construct a candidate solution, nodes are sampled sequentially from top to bottom. Each node a in the search tree maintains three statistics: (1) the visit count of the node, denoted as nan_a; (2) the cumulative reward of all solutions containing node a, denoted as LaL_a; (3) the minimum reward value among all solutions containing node a, denoted as LaminL_a^min. To balance exploration and exploitation, we adopt the Upper Confidence Bound applied to Trees (UCT) strategy [46]. At each step i, the node a in layer i is selected by maximizing the following confidence bound, derived from the Chernoff–Hoeffding inequality: acan=argmaxa∈A(v¯a+Clog∑b∈Anbna).a_can= _a∈ A ( v_a+C _b∈ An_bn_a ). (5) where C is a hyperparameter controlling the trade-off between exploration and exploitation; A denotes the set of sibling nodes sharing the same parent as node a at layer i; v¯a v_a is the estimated value of node a; nan_a is the visit count of node a; and nbn_b is the visit count of a sibling node b∈Ab∈ A. The value v¯a v_a is defined as: v¯a=−(Lamin+(L∣a))/2 v_a=-(\,L_a^min+E(L a)\,)/2 (6) where LaminL_a^min denotes the minimum HPWL value among all solutions containing node a, and (L∣a)E(L\! \!a) represents the expected HPWL of solutions containing node a. As illustrated in Fig. 2, the branch highlighted in the blue rectangle corresponds to the selected candidate solution can π_can. Once a complete solution can π_can is sampled, order exchange is performed. Order Exchange. To resolve the issue of fixed macro ordering, an order exchange operation is performed prior to the simulation and rollout. For the selected candidate solution can π_can, represented as a sequence πii=1N\ _i\_i=1^N, K distinct indices are generated by random uniform sampling from the set 1,⋯,N\1,·s,N\. The sampled K indices are utilized to determine the macros to be swapped. These macros are subsequently relocated to the terminal position of the predefined sequence. This operation splits the solution into two complementary subsquence: sub π_sub (the sampled macros) and can−sub π_can- π_sub (the remaining macros). Subsequently, the subsequence sub π_sub undergoes local search with rollouts, while can−sub π_can- π_sub remains unchanged. Consider an illustrative case with K=2K=2, assuming that the randomly sampled indices are 1,3\1,3\ (see Fig. 2). The macros corresponding to indices 11 and 33 are swapped with the macros at indices N−1N-1 and N, respectively, resulting in a new sequence order N−1,2,N,4,⋯,N−2,1,3\N-1,2,N,4,·s,N-2,1,3\. The two complementary subsquence are sub=π1,π3 π_sub=\ _1, _3\ and can−sub=πN−1,π2,πN,π4,⋯,πN−2 π_can- π_sub=\ _N-1, _2, _N, _4,·s, _N-2\. Simulation. The purpose of the simulation in this work is to replicate the state where the sequence can−sub π_can- π_sub is placed. Specifically, the macros are placed on the canvas in the order defined by indices N−1,2,N,4,⋯,N−2\N-1,2,N,4,·s,N-2\, following the placement strategy derived from can−sub π_can- π_sub. Notably, the placement process does not require explicit constraint calculations, as the selected solution can π_can is inherently valid and satisfies all necessary constraints. As illustrated in Fig. 2-a, all macros except for cells 1 and 3 are directly placed at their designated positions according to the given strategy. Macros 1 and 3, however, are reserved for multiple rollouts in the subsequent stage. Rollout. The rollout phase optimizes the position of macros in subsequence sub π_sub based on the simulation result and a heuristic strategy. During the rollout process, the macros in subsequence sub π_sub are placed sequentially on the canvas, guided by simulation results, while ensuring that no overlaps are violated. Once all macros in sub π_sub are placed, a new sequence πN−1,π2,πN,π4,⋯,πN−2,π1′,π3′\ _N-1, _2, _N, _4,·s, _N-2, _1 , _3 \ is acquired, which is slightly modified compared to the original sequence can π_can. Due to the interchangeable nature of macro placement, the new sequence can be equivalently expressed as ′=π1′,π2,π3′,π4,⋯,πN−2,πN−1,πN π =\ _1 , _2, _3 , _4,·s, _N-2, _N-1, _N\. Then, the HPWL L′L of the new solution ′ π is computed to evaluate its quality. To accelerate the local search process, multiple rollouts ii=1R\ π_i\_i=1^R can be performed based on a single simulation. Finally, the optimal solution t∗ π_t^* with the best HPWL is selected, ensuring that Lt∗=minL1,⋯,LRL_t^*= \L_1,·s,L_R\. Fig. 2-b and 2-c illustrate the detailed procedure of multiple rollouts. The selection rule is formally defined as: t∗=argmini∈ii=1RL(i) π_t^*= π_i∈\ π_i\_i=1^R \,L( π_i) (7) Update. In this process, we update the search tree from top to bottom. If the node corresponding to t∗ π_t^* already exists in the tree, the properties of the node need to be updated. If the corresponding node does not exist in the search tree, then a new node is constructed and initialized. Its parent node is the node corresponding to its previous index. The node is updated as follows: na=na+1 n_a=n_a+1 (8) La=La+Lt∗ L_a=L_a+L_t^* Lamin=min(Lamin,Lt∗). L_a^min= (L_a^min,L_t^*). where nan_a represents the visit count of node a, LaL_a denotes the cumulative HPWL and LaminL_a^min tracks the minimum observed HPWL. Algorithm 1 RollPlace Algorithm 0: Circuit macros V, Circuit netlist E, initialized tree T, search round T, sampling count K, rollout count R 0: Optimized placement solution ∗ π^* 1: for t←1t← 1 to T do 2: Sample a candidate solution can∼ π_can node by node with (5). 3: K distinct indices are generated by random uniform sampling from the set 1,⋯,N\1,·s,N\. 4: Exchange ordering of the last K macros with the selected K macros. 5: for j←1j← 1 to N−KN-K do 6: Keep the macro in the indice j of new sequence order with its original position. 7: end for 8: for r←1r← 1 to R do 9: for j←N−K+1j← N-K+1 to N do 10: Place the macro in the indice j of new sequence with policy from heuristic function FjF_j. 11: end for 12: Calculate HPWL LrL_r and record new solution r π_r. 13: end for 14: Select the best solution t∗ π_t^* according to (7). 15: Update tree T with the best solution t∗ π_t^*. 16: end for 17: return The best placement solution ∗ π^* in T IV-E Heuristic Function Consider an ordered sequence m1,m2,⋯,mN\m_1,m_2,·s,m_N\, where the positions of the first i−1i-1 macros m1,m2,⋯,mi−1\m_1,m_2,·s,m_i-1\ have already been determined on the placement canvas. The heuristic function FiF_i is computed as the Hadamard product of position mask PiP_i and wire mask WiW_i, i.e., by Fi=Pi⊙WiF_i=P_i W_i. Both PiP_i and WiW_i are matrices of size M×M× M whose values are dynamically generated based on the current placement result of m1,⋯,mi−1\m_1,·s,m_i-1\. The placement policy for macro mim_i is defined as a uniform probability distribution over all coordinates (x,y)(x,y) that yield the minimal values in FiF_i. During the rollout process, this policy is applied iteratively through sequential sampling until all N macros are placed on the grid. WireMask-EA [4] adopts a greedy strategy by selecting the nearest position within the candidate grid. In contrast, our approach employs a uniform probability distribution to explore a broader range of possibilities, thereby optimizing for better HPWLs. The following subsections provide a brief description of PiP_i and WiW_i. For a detailed description, please refer to [2]. Position Mask. PiP_i identifies legal grid positions for macro mim_i, ensuring compliance with overlap constraints and canvas boundary limits. It is represented as a binary 2D grid 1,∞M×M\1,∞\^M× M, where ∞ indicates an illegal position and 11 denotes a legal position. TABLE I: Comparisons of HPWL (×105× 10^5). Lower HPWL values indicate better placement quality. Results for DeepPlace are sourced from [5], while all other methods are evaluated by executing their respective open-source implementations with five distinct random seeds to ensure statistical reliability. For our proposed method, the minimum HPWL values achieved at 500500 and 10001000 optimization steps are recorded. Performance metrics are reported as mean values with standard deviations (mean± ). The best-performing results are highlighted in bold, while the second-best results are marked in brown. Method adaptec1 adaptec2 adaptec3 adaptec4 bigblue1 bigblue2 bigblue3 bigblue4 DREAMPlace 13.80±0.5713.80± 0.57 40.57±3.0640.57± 3.06 62.34±0.6162.34± 0.61 353.95±43.76353.95± 43.76 7.38±1.487.38± 1.48 77.55±9.6377.55± 9.63 86.53±3.5686.53± 3.56 112.95±4.03112.95± 4.03 DeepPlace 19.91±2.1319.91± 2.13 203.51±6.27203.51± 6.27 347.16±4.32347.16± 4.32 311.86±56.74311.86± 56.74 23.33±3.6523.33± 3.65 11.38±0.2011.38± 0.20 430.48±12.18430.48± 12.18 433.90±5.26433.90± 5.26 MaskPlace 7.56±0.207.56± 0.20 71.13±3.9371.13± 3.93 106.00±4.04106.00± 4.04 81.56±3.3481.56± 3.34 3.16±0.133.16± 0.13 10.69±0.8810.69± 0.88 82.55±6.5682.55± 6.56 130.15±10.94130.15± 10.94 ChiPFormer 7.40±0.097.40± 0.09 72.32±5.4172.32± 5.41 80.05±0.8780.05± 0.87 68.44±1.2968.44± 1.29 3.08±0.013.08± 0.01 7.24±0.377.24± 0.37 89.36±2.1089.36± 2.10 94.90±2.5094.90± 2.50 WireMask-EA 6.23±0.096.23± 0.09 60.33±3.6760.33± 3.67 63.04±1.7763.04± 1.77 64.99±1.1764.99± 1.17 2.17±0.022.17± 0.02 6.25±0.246.25± 0.24 66.79±5.2666.79± 5.26 87.81±3.3087.81± 3.30 EfficientPlace 5.99±0.065.99± 0.06 44.10±1.6444.10± 1.64 60.29±1.7360.29± 1.73 59.46±1.60 59.46± 1.60 2.41±0.032.41± 0.03 4.88±0.97 4.88± 0.97 77.90±11.3377.90± 11.33 88.01±2.7188.01± 2.71 RollPlace 5.98±0.11 [rgb]0.75,0.5,0.255.98± 0.11 39.59±4.67 [rgb]0.75,0.5,0.2539.59± 4.67 58.03±3.27 [rgb]0.75,0.5,0.2558.03± 3.27 67.19±1.8767.19± 1.87 2.05±0.04 [rgb]0.75,0.5,0.252.05± 0.04 5.09±0.145.09± 0.14 55.94±5.79 [rgb]0.75,0.5,0.2555.94± 5.79 76.26±3.26 [rgb]0.75,0.5,0.2576.26± 3.26 RollPlace(1k) 5.93±0.07 5.93± 0.07 34.83±1.81 34.83± 1.81 54.88±3.08 54.88± 3.08 64.66±3.49 [rgb]0.75,0.5,0.2564.66± 3.49 2.05±0.03 2.05± 0.03 5.02±0.21 [rgb]0.75,0.5,0.255.02± 0.21 53.56±7.31 53.56± 7.31 69.67±2.70 69.67± 2.70 Wire Mask. WiW_i quantifies the HPWL increment caused by the placement of macro mim_i on the canvas. It is represented as a continuous-valued 2D grid [0,1]M×M[0,1]^M× M, where the value in each grid corresponds to the normalized HPWL increase if the macro mim_i is placed on the canvas grid. V Experiments V-A Macro Placement Experimental Results (a) adaptec1 (b) adaptec2 (c) adaptec3 (d) adaptec4 (e) bigblue1 (f) bigblue2 (g) bigblue3 (h) bigblue4 Fig. 4: Convergence analysis of the best HPWL values (×105× 10^5) for RollPlace, EfficientPlace and WireMask-EA across optimization steps. Solid lines denote mean values, while shaded regions represent standard deviation intervals derived from five independent trials with distinct random seeds. We perform a comprehensive evaluation using the ISPD2005 benchmarks [47], which are widely utilized for macro placement tasks, particularly in recent ML-based research. While the original ISPD2005 benchmarks provide predefined fixed positions for all macros, our experimental setup deviates from this configuration by disregarding the fixed macro positions and excluding standard cell placement, in alignment with recent methodologies. Our framework is rigorously compared against state-of-the-art methodologies, including DeepPlace [48], DREAMPlace [30], MaskPlace [2], ChiPFormer [3], WireMask-EA [4], and EfficientPlace [5], across all ISPD2005 benchmark circuits, i.e., adaptec1−adaptec4adaptec1-adaptec4 and bigblue1−bigblue4bigblue1-bigblue4. Due to the computational complexity caused by the large number of macros in bigblue2bigblue2 (23,084 macros) and bigblue4bigblue4 (8,170 macros), we employ the sampling method proposed in [5], selecting 256256 macros for bigblue2bigblue2 and 1,0241,024 macros for bigblue4bigblue4, respectively. Within these experiments, ChiPFormer [3] processes a subset of macros during placement, which may result in overlaps. However, its metrics are calculated without addressing these overlaps. In contrast, metrics for other methods are calculated by ensuring complete macro placement without any overlap. For the RollPlace algorithm, we adopt the following parameter settings: 20 initial placements are used in total, and 10–50 macros are randomly selected in each iteration to execute the rollout strategy, with rollout repeated 30 times. Additionally, we conduct supplementary experiments using Monte Carlo rollout search with two iteration counts (500 and 1000 iterations, respectively) to further validate the effectiveness of RollPlace. Table I summarizes the detailed macro placement results across five distinct random seeds, where the objective is to minimize MacroHPWL. The experimental results demonstrate that RollPlace significantly outperforms recent state-of-the-art approaches on six out of eight benchmark circuits. On the other two benchmarks, RollPlace does not achieve the best HPWL, but it consistently attains the second-best values, slightly inferior to EfficientPlace. Notably, our fine-tuning framework demonstrates an average HPWL reduction of around 30%30\% compared to initial values, highlighting its superior optimization capabilities. These results confirm RollPlace’s exceptional performance in solving macro placement problems, particularly its ability to surpass recent fixed-order methodologies via adaptive optimization. Fig. 5: Visualization of intermediate placement results during the RollPlace search process on adaptec2adaptec2 benchmark. The red rectangle highlights macros that have shifted positions relative to the prior figure, while the blue rectangle indicates macros maintaining their positions. Fig. 4 illustrates a comparative analysis of the convergence behavior among RollPlace, EfficientPlace, and WireMask-EA, tracking the evolution of best HPWL values across runtime iterations. The results show that RollPlace exhibits superior optimization efficiency, characterized by notably faster convergence and more stable performance. Additionally, the stability of the final HPWL values across multiple runs highlights the robustness of our framework. To thoroughly analyze the optimization dynamics of RollPlace, we systematically sampled eight intermediate placement solutions during the search process. Fig. 5 visually depicts the progressive refinement of the circuit adaptec2adaptec2 layouts during optimization. The results illustrate that the positions of macros exhibit gradual but significant adjustments as the optimization progresses, particularly in the early and middle search stages. These findings confirm the effectiveness of RollPlace in exploring the solution space. We also compare the visualizations of optimal layouts for circuit adaptec2adaptec2 between RollPlace and other methods, as shown in Fig. 6. Additionally, we report the time consumption of each algorithm in the macro placement task. The time consumption by ChiPFormer only includes the fine-tuning time and excludes the training time on offline placement data. For MaskPlace, the reported time only includes the time required to deploy 128 macros under default conditions. DREAMPlace solves the Poisson equation and uses the deep learning toolkit to accelerate the solution process, so its runtime is typically measured in seconds. As shown in Table I, the runtime of our method remains within an acceptable range compared to other AI-based algorithms. All experiments were conducted on a single machine with NVIDIA GeForce RTX 2080 Ti GPUs and an Intel(R) Xeon(R) Gold 6226R CPU @ 2.90 GHz. TABLE I: Comparison of time consumption (in minutes) for macro placement across all algorithms. DREAMPlace leverages GPU acceleration to solve the placement problem. For time consumption metrics, a smaller value indicates superior performance. Method adaptec1 adaptec2 adaptec3 adaptec4 bigblue1 bigblue2 bigblue3 bigblue4 Traditional DREAMPlace 0.340.34 0.450.45 0.610.61 0.700.70 0.340.34 6.766.76 1.571.57 2.492.49 AI-based MaskPlace 120120 172172 132132 119119 104104 103103 163163 132132 ChiPFormer 1616 2121 2222 2121 1919 1919 2222 2929 WireMask-EA 184184 7171 4444 7878 3131 8080 231231 324324 EfficientPlace 7171 116116 132132 236236 8383 3030 255255 123123 RollPlace 3535 6161 5757 8080 3030 3838 155155 156156 RollPlace(1k) 7171 136136 102102 166166 6868 5858 237237 236236 Fig. 6: Macro placement visualization for adaptec2adaptec2 benchmark comparing RollPlace with five recent methods. Blue rectangles denote macros. The placement quality is evaluated through HPWL value, Lower HPWL values indicate superior performance. (a) DREAMPlace 4.007×1064.007× 10^6 (b) MaskPlace 7.514×1067.514× 10^6 (c) ChiPFormer 6.501×1066.501× 10^6 (d) WireMask-EA 5.504×1065.504× 10^6 (e) EfficientPlace 4.326×1064.326× 10^6 (f) RollPlace 3.705×1063.705× 10^6 (g) RollPlace (1k) 3.449× 3.449× 10^6 V-B Congestion Analysis In addition to wirelength optimization, congestion and density serve as critical metrics for assessing placement quality. While density metrics are not explicitly reported here due to RollPlace’s strict non-overlap hard constraints during placement, we provide a comprehensive congestion analysis. Table I compares placement congestion metrics across state-of-the-art methods, including DeepPlace [48], DREAMPlace [30], MaskPlace [2], ChiPFormer [3], WireMask-EA [4], EfficientPlace [5], and RollPlace. All congestion values are calculated using the RUDY algorithm [49]. The experimental results demonstrate RollPlace’s superior congestion optimization capability. Specifically, RollPlace achieves the best congestion values in seven out of eight benchmark circuits and consistently maintains the second-best performance in seven out of eight benchmarks. This performance highlights RollPlace’s ability to simultaneously optimize both wirelength and congestion metrics, despite its primary focus on HPWL minimization. The observed congestion reduction aligns with previous findings of Shi et al. [4], confirming that effective wirelength optimization can inherently lead to improved congestion characteristics. TABLE I: Comparisons of congestion metrics. We standardize the best congestion values to 11 for a direct comparison. These metrics are calculated directly from the results in Table I using the RUDY algorithm without modifications. Note that DeepPlace results are excluded due to unavailable placement data. Lower values indicate superior congestion performance. The best-performing results are highlighted in bold, while the second-best results are marked in brown. Method adaptec1 adaptec2 adaptec3 adaptec4 bigblue1 bigblue2 bigblue3 bigblue4 DREAMPlace 3.78±0.53.78± 0.5 1.14±0.08 [rgb]0.75,0.5,0.251.14± 0.08 1.15±0.021.15± 0.02 2.06±0.422.06± 0.42 9.74±2.019.74± 2.01 3.64±0.073.64± 0.07 1.71±0.081.71± 0.08 1.83±0.051.83± 0.05 MaskPlace 2.81±0.072.81± 0.07 1.71±0.121.71± 0.12 1.40±0.071.40± 0.07 1.12±0.041.12± 0.04 4.42±0.604.42± 0.60 2.24±0.142.24± 0.14 1.22±0.051.22± 0.05 1.65±0.111.65± 0.11 ChiPFormer 4.91±0.614.91± 0.61 1.98±0.121.98± 0.12 1.14±0.021.14± 0.02 1.01±0.011.01± 0.01 1.81±0.031.81± 0.03 1.39±0.121.39± 0.12 1.30±0.061.30± 0.06 1.26±0.091.26± 0.09 WireMask-EA 1.07±0.031.07± 0.03 1.94±0.151.94± 0.15 1.11±0.041.11± 0.04 1.06±0.041.06± 0.04 1.42±0.081.42± 0.08 1.47±0.061.47± 0.06 1.25±0.031.25± 0.03 1.21±0.051.21± 0.05 EfficientPlace 1.06±0.041.06± 0.04 1.27±0.111.27± 0.11 1.08±0.031.08± 0.03 1.02±0.021.02± 0.02 1.52±0.071.52± 0.07 1.00±0.04 1.00± 0.04 1.56±0.321.56± 0.32 1.11±0.021.11± 0.02 RollPlace 1.00±0.04 1.00± 0.04 1.14±0.221.14± 0.22 1.04±0.06 [rgb]0.75,0.5,0.251.04± 0.06 1.00±0.03 1.00± 0.03 1.02±0.13 [rgb]0.75,0.5,0.251.02± 0.13 1.15±0.041.15± 0.04 1.10±0.09 [rgb]0.75,0.5,0.251.10± 0.09 1.09±0.06 [rgb]0.75,0.5,0.251.09± 0.06 RollPlace(1k) 1.03±0.11 [rgb]0.75,0.5,0.251.03± 0.11 1.00±0.08 1.00± 0.08 1.00±0.06 1.00± 0.06 1.00±0.05 [rgb]0.75,0.5,0.251.00± 0.05 1.0±0.01 1.0± 0.01 1.14±0.06 [rgb]0.75,0.5,0.251.14± 0.06 1.00±0.11 1.00± 0.11 1.00±0.06 1.00± 0.06 V-C Full Placement Analysis Existing studies commonly employ DREAMPlace [30] to replace macros within the full placement workflow. However, this approach often leads to significant deviations between the final macro positions and algorithm’s macro placement results. While DREAMPlace demonstrates strength in macro placement, such workflows inadequately assess the efficacy of dedicated macro layout optimization algorithms. To address this, inspired by DeepPlace [48] and WireMask-EA, we propose a two-stage placement strategy for full placement tasks: (1) exclusively optimizing macro placement without considering any standard cells, (2) fixing the optimized macro positions, then employing DREAMPlace to place the remaining standard cells and perform legalization. We exclude bigblue2bigblue2 and bigblue4bigblue4 from the full placement experiments because their macro placement configurations did not include all available macros. Through extensive experimentation with the previous independent workflow, we find that the HPWL values of full placement and macro placement are not strictly proportional. Specifically, a smaller macro placement HPWL value does not invariably lead to a better full placement HPWL value. This phenomenon is illustrated by the green curve in Fig. 7, which shows the evolving relationship between macro placement and full placement HPWL throughout the optimization process. This weaker correlation in the independent workflow served as the impetus for developing our novel collaborative optimization strategy. Fig. 7: Comparison of HPWL relationship between macro placement and full placement on adaptec3adaptec3 under different workflows. The green curve reflects HPWL trends across running steps in the independent workflow, whereas the orange curve captures HPWL trends in the proposed collaborative optimization process. (a) Macro placement (b) Full placement The collaborative workflow proceeds as follows: (1) Place macros with RollPlace while omitting macro HPWL calculations, (2) after all macros are placed on the canvas, place all standard cells using DREAMPlace, and (3) calculate full placement HPWL value to replace the macro HPWL value and propagate this metric to the search tree for iterative refinement. As illustrated by the orange curve in Fig. 7, this approach establishes a positive correlation between macro HPWL and full placement HPWL. The results indicate that when optimizing HPWL for full placement, our collaborative method concurrently improves HPWL for macro placement, yielding more consistent and predictable optimization outcomes. TABLE IV: Comparisons of full placement HPWL results (×107× 10^7). Lower HPWL values indicate superior performance. Data for DeepPlace [48] are obtained from [4], while RollPlace results are generated via our full placement workflow. Results for other methods are derived from the workflow described above. The best-performing results are highlighted in bold, while the second-best results are marked in brown. Method adaptec1 adaptec2 adaptec3 adaptec4 bigblue1 bigblue3 DeepPlace 8.288.28 12.3312.33 23.2423.24 23.4023.40 14.1014.10 46.8646.86 MaskPlace 11.37±0.1311.37± 0.13 13.29±0.5813.29± 0.58 26.88±1.5026.88± 1.50 25.11±0.5225.11± 0.52 11.30±0.8111.30± 0.81 54.94±1.3254.94± 1.32 ChiPFormer 8.44±0.548.44± 0.54 12.05±0.9312.05± 0.93 27.05±1.1427.05± 1.14 23.76±0.6823.76± 0.68 9.70±0.269.70± 0.26 52.90±2.5052.90± 2.50 WireMask-EA 10.96±0.3010.96± 0.30 13.55±2.1013.55± 2.10 27.02±1.5027.02± 1.50 25.96±2.0725.96± 2.07 12.28±2.6712.28± 2.67 57.90±6.3357.90± 6.33 EfficientPlace 11.08±0.5211.08± 0.52 12.98±0.3712.98± 0.37 27.90±1.1227.90± 1.12 26.85±1.7326.85± 1.73 11.14±0.5111.14± 0.51 53.63±11.0153.63± 11.01 DREAMPlace 7.43 [rgb]0.75,0.5,0.257.43 8.42 [rgb]0.75,0.5,0.258.42 20.79 [rgb]0.75,0.5,0.2520.79 17.90 [rgb]0.75,0.5,0.2517.90 9.03 [rgb]0.75,0.5,0.259.03 30.71 [rgb]0.75,0.5,0.2530.71 RollPlace 7.28±0.06 7.28± 0.06 7.62±0.11 7.62± 0.11 16.99±0.20 16.99± 0.20 17.21±0.37 17.21± 0.37 8.84±0.04 8.84± 0.04 29.51±0.16 29.51± 0.16 V-D Full Placement Experimental Results To evaluate the effectiveness of RollPlace in full placement tasks, we perform extensive experiments on the ISPD 2005 benchmarks [47], comparing RollPlace with five recent methods, including MaskPlace [2], ChiPFormer [3], WireMask-EA [4], and EfficientPlace [5]. While all these methods except DREAMPlace employ diverse workflows, they exhibit a shared limitation: the absence of collaborative optimization between macro placement and standard cell placement. To ensure an equitable comparison, we unify their evaluation under a standardized framework comprising four steps: (1) Optimize macro placement until the predefined run steps, (2) place standard cells with DREAMPlace, leveraging the finalized macro layout, (3) perform legalization to ensure design rule compliance, and (4) calculate the full placement HPWL as the final metric. The results of DREAMPlace come from placing standard cells with DREAMPlace based on the original macro positions. In contrast, RollPlace utilizes our proposed collaborative optimization workflow and initializes with the original macro positions from the ISPD 2005 benchmarks. The results of other algorithms come from the above process. Table IV reports results for mixed-size placement, where the objective is to minimize the HPWL of all cells (macros + standard cells). The experimental results demonstrate RollPlace’s superior performance in full placement improvement. Our method consistently achieves state-of-the-art results across all benchmark circuits, outperforming recent approaches. This remarkable performance not only validates the effectiveness of our collaborative optimization strategy but also highlights RollPlace’s potential as a robust solution for modern placement challenges. The consistent improvement across diverse benchmarks suggests that the integration of macro and standard cell placement optimization in a unified framework is crucial for achieving optimal placement quality. V-E End-to-End Evaluation The primary objective of the EDA workflow is to optimize the final PPA metrics. To evaluate the effectiveness of our method within a complete EDA workflow, we adopt open-source datasets. Specifically, we use 19 benchmarks from ChiPBench [50] at the NanGate45 (NG45) technology node. Following the ChiPBench methodology, we construct an end-to-end evaluation process using OpenROAD [9] and report the final metrics. Since ML-based algorithms, such as WireMask-EA and EfficientPlace, are implemented based on the Bookshelf file format, it is necessary to convert LEF/DEF files into the Bookshelf format during the macro placement stage. Following ChiPBench, we employ the OpenROAD flow for all steps prior to macro placement and then convert the intermediate results into the Bookshelf format. After completing macro placement, the results are converted back into the LEF/DEF format, and the subsequent steps are performed using OpenROAD. In contrast, DREAMPlace and Hier-RTLMP natively support the LEF/DEF format, eliminating the need for format conversion. The evaluation reports two categories of metrics. The final design PPA metrics include worst negative slack (WNS (ns)), total negative slack (TNS (ns)), the number of violating paths (NVP), Power (nW), and Area (μm2μ m^2). The intermediate surrogate metrics include Congestion (%\%), Wirelength (μmμ m), HPWL (μmμ m), and MacroHPWL (μmμ m). For detailed statistics of each benchmark and the complete evaluation flow, please refer to [9, 50]. Different from the workflow used for the ISPD2005 benchmarks, this study employs a modified procedure. First, hMetis [51] is applied to cluster standard cells into 64 partitions. For each cluster, the pins of its constituent standard cells are mapped to the geometric center of the cluster’s bounding box. These clustered partitions are then treated as macros and subjected to the macro placement task. After that, the placement results are converted back to the LEF/DEF format, and the subsequent stages of the design flow are executed using OpenROAD. All experimental results are summarized in Table VI. The final placement results for the bp_fe38bp\_fe38 benchmark across all algorithms are illustrated in Fig. 8. To provide an intuitive comparison of how different algorithms affect various performance metrics, we ranked the five algorithms for each metric (with 1 representing the best and 5 the worst). The average ranking of each algorithm across all benchmarks is then computed. The final average ranking results are summarized in Table V. Two algorithms demonstrate relatively strong overall performance. As shown in Table V, our proposed RollPlace achieves the best average ranking in four metrics: HPWL, congestion, wirelength, and area. In contrast, Hier-RTLMP achieves the best average ranking in five other metrics: regularity, WNS, TNS, NVP, and power. This indicates that our algorithm provides significant advantages in tasks related to wirelength optimization, while Hier-RTLMP excels at capturing design dataflow. Furthermore, our method achieves competitive results in regularity, WNS, TNS, and power, suggesting that it also offers certain advantages in timing optimization under the given workflow. TABLE V: Average rankings of final design PPA metrics across all benchmarks. For all metrics, a smaller ranking value indicates better performance (with 1 representing the best performance and 5 corresponding to the worst). The best-performing results are highlighted in bold, while the second-best results are marked in brown. Method MacroHPWL Regularity HPWL Congestion Wirelength WNS TNS NVP Power Area WireMaks-EA 2.42 2.42 3.743.74 3.843.84 4.004.00 4.114.11 3.793.79 3.583.58 3.583.58 3.633.63 3.843.84 EfficientPlace 2.47 [rgb]0.75,0.5,0.252.47 3.533.53 3.793.79 3.583.58 3.583.58 3.113.11 3.583.58 3.423.42 3.263.26 3.533.53 DREAMPlace 2.632.63 3.473.47 2.742.74 2.74 [rgb]0.75,0.5,0.252.74 2.742.74 2.892.89 2.952.95 2.47 [rgb]0.75,0.5,0.252.47 2.792.79 3.053.05 Hier-RTLMP 3.633.63 1.37 1.37 2.47 [rgb]0.75,0.5,0.252.47 2.792.79 2.58 [rgb]0.75,0.5,0.252.58 2.37 2.37 2.05 2.05 1.79 1.79 1.74 1.74 2.32 [rgb]0.75,0.5,0.252.32 RollPlace 3.843.84 2.89 [rgb]0.75,0.5,0.252.89 2.16 2.16 1.79 1.79 2.00 2.00 2.84 [rgb]0.75,0.5,0.252.84 2.84 [rgb]0.75,0.5,0.252.84 2.792.79 2.47 [rgb]0.75,0.5,0.252.47 2.26 2.26 TABLE VI: Comparisons of the final design PPA metrics and intermediate surrogate metrics. All designs are synthesized and implemented using the NanGate45 open-source technology library. The best-performing results are highlighted in bold, while the second-best results are marked in brown. Benchmark Method Intermediate Metrics PPA Metrics Placement Metrics Route Metrics Timing Performance Power ↓ Area ↓ MacroHPWL ↓ Regularity ↓ HPWL ↓ Congestion ↓ Wirelength ↓ WNS ↑ TNS ↑ NVP ↓ ariane133 WireMask-EA 155475 [rgb]0.75,0.5,0.25155475 140896140896 65072826507282 0.2580.258 76676887667688 −0.298-0.298 −416.014-416.014 24042404 0.3520.352 385588385588 EfficientPlace 149649 9265892658 63911016391101 0.2550.255 75857507585750 −0.078 -0.078 −25.788 -25.788 959 0.3510.351 383901 [rgb]0.75,0.5,0.25383901 DREAMPlace 190694190694 87486 [rgb]0.75,0.5,0.2587486 5806250 0.233 0.233 6949059 −0.195-0.195 −113.649-113.649 16561656 0.345 [rgb]0.75,0.5,0.250.345 382488 Hier-RTLMP 568103568103 65804 65467896546789 0.2660.266 76936587693658 −0.114 [rgb]0.75,0.5,0.25-0.114 −48.149 [rgb]0.75,0.5,0.25-48.149 1052 [rgb]0.75,0.5,0.251052 0.342 0.342 389598389598 RollPlace 270120270120 118370118370 6334449 [rgb]0.75,0.5,0.256334449 0.252 [rgb]0.75,0.5,0.250.252 7495264 [rgb]0.75,0.5,0.257495264 −0.185-0.185 −144.404-144.404 16731673 0.3520.352 384551384551 ariane136 WireMask-EA 157147 [rgb]0.75,0.5,0.25157147 110008110008 69633586963358 0.3440.344 1014276810142768 −1.812-1.812 −2262.28-2262.28 49284928 0.4090.409 396286396286 EfficientPlace 155278 128512128512 65370156537015 0.2620.262 77634147763414 −0.163 -0.163 −117.868 [rgb]0.75,0.5,0.25-117.868 1463 [rgb]0.75,0.5,0.251463 0.378 [rgb]0.75,0.5,0.250.378 392452392452 DREAMPlace 195351195351 84820 [rgb]0.75,0.5,0.2584820 5735794 0.234 0.234 6942093 −0.170 [rgb]0.75,0.5,0.25-0.170 −87.943 -87.943 1203 0.376 0.376 389967 Hier-RTLMP 525799525799 74380 63951006395100 0.2630.263 75883977588397 −0.245-0.245 −210.549-210.549 19431943 0.3790.379 397250397250 RollPlace 261447261447 9496094960 6115838 [rgb]0.75,0.5,0.256115838 0.249 [rgb]0.75,0.5,0.250.249 7389673 [rgb]0.75,0.5,0.257389673 −0.392-0.392 −418.008-418.008 21942194 0.3830.383 391100 [rgb]0.75,0.5,0.25391100 black_parrot WireMask-EA 20396 [rgb]0.75,0.5,0.2520396 2252722527 91654049165404 0.4720.472 1096482210964822 −4.554 -4.554 −171.518 [rgb]0.75,0.5,0.25-171.518 19551955 0.4980.498 535727535727 EfficientPlace 19818 1959419594 98242889824288 0.5070.507 1175517911755179 −4.718-4.718 −292.413-292.413 16781678 0.5120.512 538959538959 DREAMPlace 3165831658 1816718167 90196949019694 0.4850.485 1125521611255216 −4.585 [rgb]0.75,0.5,0.25-4.585 −222.481-222.481 1545 [rgb]0.75,0.5,0.251545 0.485 0.485 530353 [rgb]0.75,0.5,0.25530353 Hier-RTLMP 2262122621 14169 8023406 [rgb]0.75,0.5,0.258023406 0.420 [rgb]0.75,0.5,0.250.420 9512238 −4.906-4.906 −99.094 -99.094 1390 0.490 [rgb]0.75,0.5,0.250.490 530012 RollPlace 4368243682 17539 [rgb]0.75,0.5,0.2517539 8007123 0.412 0.412 9591922 [rgb]0.75,0.5,0.259591922 −4.778-4.778 −221.091-221.091 29032903 0.490 [rgb]0.75,0.5,0.250.490 531889531889 bp_be WireMask-EA 11250 45454545 34204293420429 0.6500.650 44499514449951 −0.818-0.818 −72.564-72.564 127 [rgb]0.75,0.5,0.25127 0.1530.153 124271124271 EfficientPlace 11654 [rgb]0.75,0.5,0.2511654 51505150 33092213309221 0.61390.6139 41860044186004 −0.799-0.799 −65.932-65.932 111 0.1490.149 123190123190 DREAMPlace 1697716977 4518 [rgb]0.75,0.5,0.254518 33771183377118 0.588 [rgb]0.75,0.5,0.250.588 42187694218769 −0.657-0.657 −51.154-51.154 111 0.146 0.146 123563123563 Hier-RTLMP 1357613576 4333 3212067 [rgb]0.75,0.5,0.253212067 0.5990.599 4087593 [rgb]0.75,0.5,0.254087593 −0.621 [rgb]0.75,0.5,0.25-0.621 −40.274 [rgb]0.75,0.5,0.25-40.274 111 0.147 [rgb]0.75,0.5,0.250.147 122479 [rgb]0.75,0.5,0.25122479 RollPlace 1426214262 54655465 3195611 0.568 0.568 3998973 −0.553 -0.553 −39.983 -39.983 111 0.147 [rgb]0.75,0.5,0.250.147 122270 bp_fe WireMask-EA 4421544215 51985198 24696362469636 0.8150.815 42307134230713 −2.469-2.469 −827.503-827.503 11931193 0.1900.190 7205672056 EfficientPlace 43871 [rgb]0.75,0.5,0.2543871 53495349 26069892606989 0.6770.677 36013803601380 −0.969-0.969 −94.775-94.775 497497 0.1820.182 7390473904 DREAMPlace 43729 4442 [rgb]0.75,0.5,0.254442 22771622277162 0.6150.615 33239723323972 −1.137-1.137 −81.975-81.975 393393 0.170 [rgb]0.75,0.5,0.250.170 71608 [rgb]0.75,0.5,0.2571608 Hier-RTLMP 4868248682 4083 2051900 0.482 0.482 2631261 −0.237 -0.237 −5.950 -5.950 96 0.167 0.167 70165 RollPlace 5179851798 45704570 2190620 [rgb]0.75,0.5,0.252190620 0.562 [rgb]0.75,0.5,0.250.562 3040182 [rgb]0.75,0.5,0.253040182 −0.867 [rgb]0.75,0.5,0.25-0.867 −77.150 [rgb]0.75,0.5,0.25-77.150 377 [rgb]0.75,0.5,0.25377 0.1710.171 7183771837 dft68 WireMask-EA 179789 4710947109 12139381213938 0.0970.097 13544871354487 −0.340-0.340 −65.007-65.007 277 [rgb]0.75,0.5,0.25277 0.2320.232 8607186071 EfficientPlace 214872 [rgb]0.75,0.5,0.25214872 4672746727 12990501299050 0.1030.103 14434201443420 −0.389-0.389 −68.607-68.607 278278 0.2380.238 8715287152 DREAMPlace 216173216173 4643446434 1124378 0.094 [rgb]0.75,0.5,0.250.094 1266514 −0.315 [rgb]0.75,0.5,0.25-0.315 −59.877 [rgb]0.75,0.5,0.25-59.877 276 0.226 0.226 86044 [rgb]0.75,0.5,0.2586044 Hier-RTLMP 513981513981 34462 17521291752129 0.1350.135 18880291888029 −0.286 -0.286 −56.865 -56.865 276 0.2320.232 8814488144 RollPlace 218560218560 42853 [rgb]0.75,0.5,0.2542853 1154247 [rgb]0.75,0.5,0.251154247 0.093 0.093 1299421 [rgb]0.75,0.5,0.251299421 −0.320-0.320 −61.098-61.098 276 0.231 [rgb]0.75,0.5,0.250.231 85669 or1200 WireMask-EA 103246103246 1810218102 884872884872 0.0730.073 10515381051538 −7.708-7.708 −309.542-309.542 149149 0.028 [rgb]0.75,0.5,0.250.028 6898268982 EfficientPlace 109239109239 17853 [rgb]0.75,0.5,0.2517853 888252888252 0.0720.072 10409271040927 −7.580-7.580 −1780.920-1780.920 16741674 0.028 [rgb]0.75,0.5,0.250.028 6778767787 DREAMPlace 72118 2625426254 838399 0.070 [rgb]0.75,0.5,0.250.070 1014607 [rgb]0.75,0.5,0.251014607 −6.040 [rgb]0.75,0.5,0.25-6.040 −255.116-255.116 115 0.0420.042 6926869268 Hier-RTLMP 115057115057 16540 884510884510 0.0710.071 10274871027487 −6.010 -6.010 −215.324 -215.324 145 [rgb]0.75,0.5,0.25145 0.027 0.027 66906 RollPlace 89244 [rgb]0.75,0.5,0.2589244 1801918019 843026 [rgb]0.75,0.5,0.25843026 0.069 0.069 995492 −6.487-6.487 −243.606 [rgb]0.75,0.5,0.25-243.606 155155 0.027 0.027 67246 [rgb]0.75,0.5,0.2567246 swerv_wrapper WireMask-EA 89410 [rgb]0.75,0.5,0.2589410 1745517455 46818694681869 0.3960.396 55592565559256 −1.412-1.412 −1344.120-1344.120 17291729 0.2700.270 232705232705 EfficientPlace 78835 1638416384 4246494 [rgb]0.75,0.5,0.254246494 0.362 [rgb]0.75,0.5,0.250.362 5064971 [rgb]0.75,0.5,0.255064971 −0.610 [rgb]0.75,0.5,0.25-0.610 −541.569 -541.569 1432 [rgb]0.75,0.5,0.251432 0.265 [rgb]0.75,0.5,0.250.265 229790 [rgb]0.75,0.5,0.25229790 DREAMPlace 101776101776 13783 [rgb]0.75,0.5,0.2513783 45063784506378 0.3690.369 53594945359494 −0.844-0.844 −645.860-645.860 15261526 0.2670.267 230232230232 Hier-RTLMP 118198118198 1673216732 3829279 0.330 0.330 4603628 −0.599 -0.599 −583.211 [rgb]0.75,0.5,0.25-583.211 14361436 0.262 0.262 226460 RollPlace 109254109254 13554 46510574651057 0.3960.396 55433655543365 −0.987-0.987 −737.212-737.212 1409 0.2830.283 231627231627 bp_multi WireMask-EA 24117 [rgb]0.75,0.5,0.2524117 1874118741 48295354829535 0.379 [rgb]0.75,0.5,0.250.379 5581405 [rgb]0.75,0.5,0.255581405 −5.483 -5.483 −2628.98 -2628.98 9225 0.535 0.535 263234 [rgb]0.75,0.5,0.25263234 EfficientPlace 2489724897 14363 [rgb]0.75,0.5,0.2514363 5244707 [rgb]0.75,0.5,0.255244707 0.4070.407 59463945946394 −5.758-5.758 −3907.67-3907.67 1006510065 0.538 [rgb]0.75,0.5,0.250.538 266985266985 DREAMPlace 3407834078 1697316973 53128445312844 0.4180.418 61466876146687 −5.591 [rgb]0.75,0.5,0.25-5.591 −3226.07-3226.07 94489448 0.5390.539 266624266624 Hier-RTLMP 22784 11794 4765293 0.376 0.376 5485683 −5.785-5.785 −2740.43 [rgb]0.75,0.5,0.25-2740.43 9409 [rgb]0.75,0.5,0.259409 0.535 0.535 262806 RollPlace 4603646036 1624316243 54560175456017 0.4080.408 61781726178172 −5.647-5.647 −2946.30-2946.30 96959695 0.538 [rgb]0.75,0.5,0.250.538 266525266525 vga_lcd WireMask-EA 53572 [rgb]0.75,0.5,0.2553572 32980 [rgb]0.75,0.5,0.2532980 1461215 0.1540.154 30363963036396 −5.387-5.387 −1839.45 [rgb]0.75,0.5,0.25-1839.45 3774 [rgb]0.75,0.5,0.253774 0.180 0.180 262468262468 EfficientPlace 45907 3921339213 1463868 [rgb]0.75,0.5,0.251463868 0.1460.146 29756372975637 −4.328-4.328 −4834.09-4834.09 93079307 0.184 [rgb]0.75,0.5,0.250.184 271819271819 DREAMPlace 5783257832 4955149551 16630691663069 0.123 0.123 2511081 −1.650-1.650 −6766.29-6766.29 2109021090 0.1940.194 255125 [rgb]0.75,0.5,0.25255125 Hier-RTLMP 101530101530 28761 17179061717906 0.132 [rgb]0.75,0.5,0.250.132 2684816 [rgb]0.75,0.5,0.252684816 −0.982 -0.982 −431.846 -431.846 3236 0.1910.191 261276261276 RollPlace 7270772707 4951349513 18360991836099 0.1370.137 27820212782021 −1.060 [rgb]0.75,0.5,0.25-1.060 −6359.71-6359.71 2098220982 0.1930.193 254758 mor1kx WireMask-EA 7827078270 2080520805 19833741983374 0.4080.408 25887342588734 −1.384-1.384 −11159.8-11159.8 1019810198 0.2540.254 155424155424 EfficientPlace 7720977209 2099220992 19641361964136 0.4050.405 25643382564338 −1.346-1.346 −10474.3 [rgb]0.75,0.5,0.25-10474.3 10092 [rgb]0.75,0.5,0.2510092 0.2570.257 155086 [rgb]0.75,0.5,0.25155086 DREAMPlace 37540 3542435424 1820175 0.382 0.382 2438671 −1.368-1.368 −11109.4-11109.4 1013410134 0.2570.257 155713155713 Hier-RTLMP 7349273492 19766 19507671950767 0.4070.407 25815612581561 −1.341 [rgb]0.75,0.5,0.25-1.341 −10384.2 -10384.2 10068 0.253 [rgb]0.75,0.5,0.250.253 154708 RollPlace 72364 [rgb]0.75,0.5,0.2572364 20431 [rgb]0.75,0.5,0.2520431 1928368 [rgb]0.75,0.5,0.251928368 0.399 [rgb]0.75,0.5,0.250.399 2546238 [rgb]0.75,0.5,0.252546238 −1.340 -1.340 −10817.2-10817.2 1017510175 0.252 0.252 155254155254 ethernet WireMask-EA 3142831428 2266622666 871709871709 0.2880.288 11006571100657 −0.192-0.192 −5.647-5.647 9090 0.117 0.117 9621696216 EfficientPlace 3284832848 1882118821 875794875794 0.2880.288 11029481102948 −0.245-0.245 −9.088-9.088 109109 0.117 0.117 96089 DREAMPlace 27200 1987019870 886057886057 0.2940.294 11226771122677 −0.094 -0.094 −4.248 [rgb]0.75,0.5,0.25-4.248 109109 0.118 [rgb]0.75,0.5,0.250.118 9638796387 Hier-RTLMP 27959 [rgb]0.75,0.5,0.2527959 13597 859826 [rgb]0.75,0.5,0.25859826 0.286 [rgb]0.75,0.5,0.250.286 1090616 [rgb]0.75,0.5,0.251090616 −0.101 [rgb]0.75,0.5,0.25-0.101 −1.138 -1.138 53 0.117 0.117 9626196261 RollPlace 3566835668 15199 [rgb]0.75,0.5,0.2515199 859207 0.285 0.285 1087237 −0.191-0.191 −5.359-5.359 88 [rgb]0.75,0.5,0.2588 0.117 0.117 96210 [rgb]0.75,0.5,0.2596210 isa_npu WireMask-EA 6807468074 1205812058 63554346355434 0.1970.197 78443777844377 −0.928-0.928 −26.758-26.758 5252 0.9440.944 998762 [rgb]0.75,0.5,0.25998762 EfficientPlace 6958269582 1275012750 63213046321304 0.1990.199 78304847830484 −0.877 -0.877 −27.015-27.015 5656 0.941 0.941 999421999421 DREAMPlace 122149122149 11866 [rgb]0.75,0.5,0.2511866 64608496460849 0.2030.203 79605187960518 −1.015-1.015 −25.337 -25.337 43 0.941 0.941 10002001000200 Hier-RTLMP 39446 10354 6190877 [rgb]0.75,0.5,0.256190877 0.196 [rgb]0.75,0.5,0.250.196 7680181 [rgb]0.75,0.5,0.257680181 −0.955-0.955 −27.691-27.691 5252 0.942 [rgb]0.75,0.5,0.250.942 998084 RollPlace 63470 [rgb]0.75,0.5,0.2563470 1316413164 6166348 0.192 0.192 7641026 −0.912 [rgb]0.75,0.5,0.25-0.912 −25.741 [rgb]0.75,0.5,0.25-25.741 47 [rgb]0.75,0.5,0.2547 0.9450.945 999129999129 ariane81 WireMask-EA 149427 [rgb]0.75,0.5,0.25149427 7631476314 58519835851983 0.3220.322 71730677173067 −0.342-0.342 −494.304-494.304 25442544 0.1900.190 341238341238 EfficientPlace 134531 7397273972 61097446109744 0.3690.369 83514968351496 −0.983-0.983 −2382.980-2382.980 34203420 0.1940.194 339517339517 DREAMPlace 206821206821 5993259932 4848578 0.267 0.267 5949468 −0.133 -0.133 −64.289 -64.289 1103 0.1890.189 336665 [rgb]0.75,0.5,0.25336665 Hier-RTLMP 330885330885 53896 54404475440447 0.3040.304 65575906557590 −0.146 [rgb]0.75,0.5,0.25-0.146 −127.447 [rgb]0.75,0.5,0.25-127.447 1639 [rgb]0.75,0.5,0.251639 0.187 [rgb]0.75,0.5,0.250.187 339833339833 RollPlace 219111219111 57129 [rgb]0.75,0.5,0.2557129 4910179 [rgb]0.75,0.5,0.254910179 0.268 [rgb]0.75,0.5,0.250.268 5977030 [rgb]0.75,0.5,0.255977030 −0.279-0.279 −148.917-148.917 16851685 0.186 0.186 336084 bp_fe38 WireMask-EA 922755922755 1968919689 3073331 [rgb]0.75,0.5,0.253073331 0.404 [rgb]0.75,0.5,0.250.404 3374605 [rgb]0.75,0.5,0.253374605 −1.459-1.459 −375.086 [rgb]0.75,0.5,0.25-375.086 616 0.112 [rgb]0.75,0.5,0.250.112 6064360643 EfficientPlace 910340 [rgb]0.75,0.5,0.25910340 2049320493 33318423331842 0.4440.444 37227903722790 −1.362 -1.362 −695.666-695.666 11311131 0.112 [rgb]0.75,0.5,0.250.112 6322663226 DREAMPlace 836309 2113921139 31271173127117 0.4150.415 34678603467860 −1.400 [rgb]0.75,0.5,0.25-1.400 −455.777-455.777 642 [rgb]0.75,0.5,0.25642 0.111 0.111 59742 Hier-RTLMP 960485960485 19504 [rgb]0.75,0.5,0.2519504 32953643295364 0.4630.463 37370523737052 −1.815-1.815 −883.540-883.540 15041504 0.111 0.111 6280762807 RollPlace 931533931533 18298 2837217 0.377 0.377 3138932 −2.076-2.076 −361.105 -361.105 642 [rgb]0.75,0.5,0.25642 0.111 0.111 59958 [rgb]0.75,0.5,0.2559958 bp_be12 WireMask-EA 785283785283 4018 36960673696067 0.5270.527 42149494214949 −0.638 [rgb]0.75,0.5,0.25-0.638 −56.489 [rgb]0.75,0.5,0.25-56.489 114 0.0770.077 9360093600 EfficientPlace 799616799616 53105310 36724313672431 0.5250.525 41755244175524 −0.804-0.804 −68.646-68.646 115 [rgb]0.75,0.5,0.25115 0.0760.076 9372793727 DREAMPlace 728422 63866386 3512250 0.486 0.486 3986750 −0.724-0.724 −67.658-67.658 114 0.075 [rgb]0.75,0.5,0.250.075 91549 [rgb]0.75,0.5,0.2591549 Hier-RTLMP 759742 [rgb]0.75,0.5,0.25759742 47584758 3527781 [rgb]0.75,0.5,0.253527781 0.5320.532 42816694281669 −0.811-0.811 −73.532-73.532 114 0.074 0.074 88021 RollPlace 801407801407 4353 [rgb]0.75,0.5,0.254353 35397993539799 0.506 [rgb]0.75,0.5,0.250.506 4005604 [rgb]0.75,0.5,0.254005604 −0.568 -0.568 −51.651 -51.651 114 0.0760.076 9304193041 bp68 WireMask-EA 1517203 65369 [rgb]0.75,0.5,0.2565369 1921383619213836 0.6960.696 2242171222421712 −2.253 [rgb]0.75,0.5,0.25-2.253 −1102.22 [rgb]0.75,0.5,0.25-1102.22 951951 0.1550.155 305872305872 EfficientPlace 16179411617941 6880968809 1940037319400373 0.6910.691 2228094322280943 −3.717-3.717 −2463.41-2463.41 16821682 0.1570.157 311245311245 DREAMPlace 1519611 [rgb]0.75,0.5,0.251519611 7143271432 1440492914404929 0.5140.514 1616370116163701 −3.029-3.029 −1161.74-1161.74 574574 0.1540.154 291142291142 Hier-RTLMP 16362201636220 51848 12356892 [rgb]0.75,0.5,0.2512356892 0.466 [rgb]0.75,0.5,0.250.466 14360494 [rgb]0.75,0.5,0.2514360494 −2.152 -2.152 −684.921 -684.921 557 0.149 0.149 281856 [rgb]0.75,0.5,0.25281856 RollPlace 15591541559154 7205772057 12007845 0.434 0.434 13937557 −3.098-3.098 −1267.47-1267.47 573 [rgb]0.75,0.5,0.25573 0.152 [rgb]0.75,0.5,0.250.152 275980 swerv_wrapper43 WireMask-EA 138792 2567725677 45142854514285 0.2190.219 52763555276355 −0.613-0.613 −452.786-452.786 10701070 0.2590.259 228524228524 EfficientPlace 149814 [rgb]0.75,0.5,0.25149814 20833 43269554326955 0.2170.217 51069415106941 −0.482 -0.482 −316.883 -316.883 987 0.255 [rgb]0.75,0.5,0.250.255 226014 [rgb]0.75,0.5,0.25226014 DREAMPlace 330670330670 3592935929 46711194671119 0.2250.225 54127705412770 −0.841-0.841 −490.785-490.785 12481248 0.2620.262 231113231113 Hier-RTLMP 198090198090 23576 [rgb]0.75,0.5,0.2523576 4208196 0.211 [rgb]0.75,0.5,0.250.211 4958294 −0.534 [rgb]0.75,0.5,0.25-0.534 −385.210 [rgb]0.75,0.5,0.25-385.210 1057 [rgb]0.75,0.5,0.251057 0.2560.256 225769 RollPlace 201904201904 3051330513 4244105 [rgb]0.75,0.5,0.254244105 0.209 0.209 5029937 [rgb]0.75,0.5,0.255029937 −0.642-0.642 −598.949-598.949 14671467 0.254 0.254 227217227217 bp_multi57 WireMask-EA 17057621705762 3973339733 4202597542025975 3.2083.208 4728742547287425 −6.406-6.406 −3801.37-3801.37 12851285 0.1840.184 478237478237 EfficientPlace 10410301041030 4273342733 68800156880015 0.5370.537 76761577676157 −2.551-2.551 −628.698-628.698 408408 0.1070.107 209585209585 DREAMPlace 523787 3784837848 74847367484736 0.5840.584 83537848353784 −3.228-3.228 −982.560-982.560 471471 0.1070.107 214791214791 Hier-RTLMP 739345 [rgb]0.75,0.5,0.25739345 25468 5677569 0.467 0.467 6343384 −1.899 -1.899 −384.005 -384.005 347 0.105 0.105 204078 RollPlace 745533745533 36651 [rgb]0.75,0.5,0.2536651 6125984 [rgb]0.75,0.5,0.256125984 0.474 [rgb]0.75,0.5,0.250.474 6739992 [rgb]0.75,0.5,0.256739992 −2.101 [rgb]0.75,0.5,0.25-2.101 −492.077 [rgb]0.75,0.5,0.25-492.077 377 [rgb]0.75,0.5,0.25377 0.106 [rgb]0.75,0.5,0.250.106 205830 [rgb]0.75,0.5,0.25205830 Fig. 8: Final placement results of different methods for the bp_fe38bp\_fe38 benchmark. For key performance metrics, a smaller WireLength indicates better routing efficiency, while larger values of WNS and TNS reflect superior timing performance. (a) WireMask-EA Wirelength=3374605 WNS=-1.459 TNS=-375.086 (b) EfficientPlace Wirelength=3722790 WNS=–1.362 TNS=-695.666 (c) DREAMPlace Wirelength=3467860 WNS=-1.400 TNS=-455.777 (d) Hier-RTLMP Wirelength=3737052 WNS=-1.815 TNS=-883.540 (e) RollPlace Wirelength=3138932 WNS=-2.076 TNS=-361.105 VI Conclusion In this paper, we propose RollPlace, a novel macro placement improvement framework that systematically enhances initial layouts through iterative local adjustments. By integrating Monte Carlo rollout search with heuristic functions, RollPlace achieves significant improvements in overall layout quality. It demonstrates remarkable versatility by seamlessly integrating with state-of-the-art standard cell placement tools such as DREAMPlace, thereby facilitating effective optimization of full placement scenarios. Extensive experiments show that RollPlace consistently outperforms recent RL and black-box optimization based algorithms, while exhibiting superior robustness across diverse benchmarks. Furthermore, our analysis highlights the inherent limitations of one-time generation in current RL-based methods. RollPlace addresses these challenges through its iterative refinement strategy, offering a promising pathway for future advancements in this domain. Despite these advancements, several limitations warrant consideration. First, similar to recent RL-based methods and the WireMask-EA approach, RollPlace encounters scalability challenges when processing benchmarks with an exceptionally large number of macros. Second, RollPlace employs only a simple wire mask as a heuristic function, without considering its impact on the quality of full placement. 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