Paper deep dive
Eco-SoC: A Sustainable VLSI Architecture for Energy-Proportional Artificial Intelligence
Jatin Chopra
Intelligence
Status: succeeded | Model: Gemma-4-26B-A4B | Prompt: intel-v1 | Confidence: 90%
Last extracted: 8/12/2026, 2:34:13 AM
Summary
The paper introduces Eco-SoC, a sustainable VLSI architecture for edge AI that utilizes Dynamic Precision-Scaling Logic (DPSL) and Thermal-Aware Power Gating (TAPG) to achieve energy-proportional computing. By dynamically adjusting bit-width precision based on activation sparsity and thermal conditions, Eco-SoC reduces switching activity by 42% and doubles the Mean Time To Failure (MTTF) of the silicon. A Life Cycle Assessment (LCA) using the Architectural Carbon footprint Tool (ACT) demonstrates that the architecture offsets its 4.8% area-related embodied carbon footprint within 1.1 years, significantly mitigating electronic waste.
Entities (8)
Relation Signals (7)
Eco-SoC → implements → Dynamic Precision-Scaling Logic
confidence 95% · We propose a hardware-level Dynamic Precision-Scaling Logic (DPSL) framework... Eco-SoC introduces the DPSL controller
Eco-SoC → implements → Thermal-Aware Power Gating
confidence 92% · by introducing a thermal-aware power gating mechanism... Eco-SoC implements a hardware-managed Thermal-Aware Power Gating (TAPG) loop.
Dynamic Precision-Scaling Logic → reduces → switching activity
confidence 90% · successfully reducing switching activity by up to 42%
Eco-SoC → synthesizedon → 7nm FinFET
confidence 90% · successfully reducing switching activity by up to 42% on a commercial 7nm FinFET process node.
Eco-SoC → doubles → Mean Time To Failure
confidence 88% · Eco-SoC doubles the projected Mean Time To Failure (MTTF) of the silicon
Dynamic Precision-Scaling Logic → controls → Systolic MAC Array
confidence 87% · dynamically clock-gating the lower significant bits of the systolic MAC array
Eco-SoC → evaluatedusing → Architectural Carbon footprint Tool
confidence 85% · providing a comprehensive Life Cycle Assessment (LCA) using the Architectural Carbon footprint Tool (ACT).
Cypher Suggestions (0)
No Cypher suggestions yet.
Abstract
Abstract:In an era defined by escalating climate change and the pervasive deployment of edge intelligence, the environmental cost of semiconductor manufacturing and operation has reached a critical threshold. As Deep Learning (DL) accelerators dominate System-on-Chip (SoC) die area, achieving true sustainability requires a paradigm shift from static worst-case efficiency to dynamic energy-proportionality. This paper introduces Eco-SoC, a highly scalable VLSI architecture co-designed specifically for sustainable artificial intelligence. We propose a hardware-level Dynamic Precision-Scaling Logic (DPSL) framework that adaptively modulates bit-width precision based on real-time activation sparsity, successfully reducing switching activity by up to 42% on a commercial 7nm FinFET process node. Furthermore, we transcend traditional Power-Performance-Area (PPA) metrics by providing a comprehensive Life Cycle Assessment (LCA) using the Architectural Carbon footprint Tool (ACT). Our synthesis demonstrates that Eco-SoC offsets its increased embodied carbon footprint (a marginal 4.8% area overhead) within 1.1 years of edge deployment. Finally, by introducing a thermal-aware power gating mechanism that mitigates localized hotspots, Eco-SoC doubles the projected Mean Time To Failure (MTTF) of the silicon, providing a tangible, scalable strategy for electronic waste (e-waste) mitigation in next-generation computing systems.
Tags
Links
- Source: https://arxiv.org/abs/2608.08761v1
- Canonical: https://arxiv.org/abs/2608.08761v1
Trouble viewing inline? Open PDF directly →
Full Text
29,181 characters extracted from source content.
Expand or collapse full text
Eco-SoC: A Sustainable VLSI Architecture for Energy-Proportional Artificial Intelligence Jatin Chopra jatin27chopra@gmail.com Microsoft CorporationRedmondWashingtonUSA Indian Institute of Technology DelhiNew DelhiIndia (2026) Abstract. In an era defined by escalating climate change and the pervasive deployment of edge intelligence, the environmental cost of semiconductor manufacturing and operation has reached a critical threshold. As Deep Learning (DL) accelerators dominate System-on-Chip (SoC) die area, achieving true sustainability requires a paradigm shift from static worst-case efficiency to dynamic energy-proportionality. This paper introduces Eco-SoC, a highly scalable VLSI architecture co-designed specifically for sustainable artificial intelligence. We propose a hardware-level Dynamic Precision-Scaling Logic (DPSL) framework that adaptively modulates bit-width precision based on real-time activation sparsity, successfully reducing switching activity by up to 42% on a commercial 7nm FinFET process node. Furthermore, we transcend traditional Power-Performance-Area (PPA) metrics by providing a comprehensive Life Cycle Assessment (LCA) using the Architectural Carbon footprint Tool (ACT). Our synthesis demonstrates that Eco-SoC offsets its increased embodied carbon footprint (a marginal 4.8% area overhead) within 1.1 years of edge deployment. Finally, by introducing a thermal-aware power gating mechanism that mitigates localized hotspots, Eco-SoC doubles the projected Mean Time To Failure (MTTF) of the silicon, providing a tangible, scalable strategy for electronic waste (e-waste) mitigation in next-generation computing systems. VLSI Design, Sustainability, Green Computing, Low-Power SoC, Life Cycle Assessment, Carbon Footprint, Thermal-Aware Design, Electronic Design Automation (EDA) †copyright: acmcopyright†journalyear: 2026†doi: 10.1145/n.n†journal: JETC†journalvolume: 1†journalnumber: 1†article: 1†publicationmonth: 10†ccs: Hardware Hardware-software codesign†ccs: Hardware Energy-aware computing†ccs: Hardware Power estimation and optimization†ccs: Hardware Self-optimizing adaptive processors 1. Introduction The rapid proliferation of edge Artificial Intelligence (AI) and the integration of deep learning micro-accelerators into smart infrastructure have catalyzed unprecedented demand for computational density. However, this growth trajectory has exposed a severe environmental vulnerability within the semiconductor industry. Modern Very Large Scale Integration (VLSI) systems present a dual sustainability challenge: an escalating demand for operational energy to train and infer complex neural networks, and a massively growing ”embodied” carbon footprint resulting from the resource-intensive manufacturing of advanced sub-10nm fabrication nodes (Grimblatt and others, 2024; Gupta and others, 2024). Historically, Electronic Design Automation (EDA) flows and computer architecture research have been ruthlessly optimized for Power, Performance, and Area (PPA) (Hennessy and Patterson, 2023). While maximizing performance-per-watt remains critical, the global mandate for a ”Sustainable World” requires a holistic view of the device lifecycle. High-performance Systems-on-Chip (SoCs) frequently operate at peak dynamic power regardless of task complexity, leading to severe energy waste. Furthermore, this static power consumption accelerates thermal degradation, precipitating premature device failure and exacerbating the global electronic waste (e-waste) crisis (Pravadelli, 2023; Mandal and others, 2024). To address the escalating climate impact of semiconductor technologies, VLSI architectures must transition from static power-efficiency to dynamic energy-proportionality. A system is energy-proportional if its power consumption scales strictly in alignment with the computational criticality and precision requirements of the immediate workload (Barroso and Hölzle, 2007). While software-level approximate computing and network quantization (e.g., INT8/INT4 weight clipping) have shown promise in reducing model sizes, these algorithmic gains frequently fail to translate into silicon-level energy reductions because the underlying multiplier-accumulator (MAC) arrays remain statically wired for worst-case, maximum-precision execution (Wang and others, 2025). To bridge this critical gap between algorithmic sparsity and hardware efficiency, this paper introduces Eco-SoC, a highly scalable VLSI architecture co-designed to minimize both operational greenhouse gas emissions (CO2eCO_2e) and embodied electronic waste. By intervening directly at the Register-Transfer Level (RTL) and clock-tree synthesis stages, Eco-SoC dynamically scales its active logic based on real-time activation data. 1.1. Primary Contributions This expanded study provides a comprehensive end-to-end evaluation of sustainable VLSI design, extending from theoretical algorithmic sparsity down to physical 7nm tape-out synthesis. The primary contributions of this work are: • Dynamic Precision-Scaling Logic (DPSL): We design and implement a novel hardware-level gating architecture that monitors activation sparsity in real-time. By dynamically clock-gating the lower significant bits of the systolic MAC array during low-precision inferencing, we demonstrate a 42% reduction in dynamic switching activity (α) compared to traditional static INT8 accelerators. • Thermal-Aware Power Profiling: We introduce a hardware-managed thermal feedback loop that forces precision down-scaling when junction temperatures (TjT_j) cross sustainable thresholds, actively preventing thermal runaway in highly dense multicore edge environments. • Comprehensive Life Cycle Assessment (LCA): Moving beyond traditional PPA, we evaluate the architecture using a cradle-to-grave carbon modeling framework. We provide mathematical formalization proving that the operational energy savings of Eco-SoC offset its increased embodied manufacturing carbon (a 4.8% die area overhead) within 1.1 years of standard deployment. • Reliability-Driven E-Waste Mitigation: By lowering the thermal envelope of the SoC, we utilize the Arrhenius physical failure models to project a 102% increase in Mean Time To Failure (MTTF), extending the device lifespan from 4.2 to 8.5 years and directly addressing the hardware replacement cycle that drives global e-waste. 2. Background and Related Work The pursuit of sustainability in computing systems has historically been confined to the domain of data center power usage effectiveness (PUE) and operational energy reduction. However, the slowing of Moore’s Law and the definitive end of Dennard Scaling have shifted the environmental bottleneck from the software and operational levels directly into the semiconductor manufacturing process (Esmaeilzadeh and others, 2011). Designing for a ”Sustainable World” now requires a multi-objective optimization problem that treats carbon emissions and device longevity as primary constraints alongside Power, Performance, and Area (PPA). 2.1. The Environmental Footprint of Advanced VLSI Nodes The environmental impact of computing hardware is broadly categorized into two phases: Operational Carbon (emissions generated from electricity consumed during the device’s active lifetime) and Embodied Carbon (emissions generated during silicon mining, wafer fabrication, packaging, and distribution). Historically, operational energy dominated the footprint of computing devices. However, as fabrication technologies have advanced to extreme ultraviolet (EUV) lithography for sub-10nm FinFET and Gate-All-Around (GAA) nodes, the energy and water intensity required to manufacture a single mm2m^2 of silicon has skyrocketed. Recent Life Cycle Assessment (LCA) studies, notably the ACT (Architectural Carbon footprint Tool) framework introduced by Gupta et al., reveal that for mobile, edge, and consumer SoCs, embodied carbon can now account for up to 70–80% of the device’s total lifetime emissions (Gupta and others, 2024). Consequently, the Semiconductor Sustainability Roadmap targets net-zero fabrication by 2030, but achieving this requires VLSI architects to design hardware that maximizes its operational lifespan to amortize the massive initial embodied carbon cost (ITRS Committee, 2025; Grimblatt and others, 2024). 2.2. Limitations of Static Approximate Computing in Green AI Artificial Intelligence, particularly Deep Neural Networks (DNNs), is notoriously resource-intensive. To mitigate the energy overhead of edge AI inferencing, the industry has widely adopted Approximate Computing and model quantization (Wang and others, 2025). Frameworks routinely compress 32-bit floating-point (FP32) weights down to 8-bit integers (INT8) or even 4-bit (INT4) representations with negligible loss in inference accuracy. However, a critical misalignment exists between algorithmic quantization and silicon execution. Standard DL accelerators and systolic arrays are synthesized with statically sized Multiplier-Accumulator (MAC) units. If a software model dynamically drops to 4-bit precision due to activation sparsity, a standard 8-bit MAC unit will still toggle its clock tree and registers for the upper zero-padded bits. This phenomenon results in unnecessary dynamic switching activity (α), wasting operational energy (Jouppi and others, 2017). While some state-of-the-art architectures implement zero-skipping (clock-gating MACs entirely when an activation is exactly zero), very few can dynamically scale their bit-width at runtime to match fluctuating precision requirements without incurring prohibitive area overheads for the control logic (Albericio and others, 2016). Eco-SoC addresses this precise limitation through its hardware-software co-designed Dynamic Precision-Scaling Logic (DPSL). 2.3. Thermal Degradation, Reliability, and Electronic Waste Beyond immediate energy consumption, the thermal profile of an SoC is the primary determinant of its physical lifespan. High-density DL accelerators generate intense, localized thermal hotspots. Sustained high junction temperatures (TjT_j) accelerate physical failure mechanisms in silicon, including Time-Dependent Dielectric Breakdown (TDDB), Electromigration (EM), and Negative Bias Temperature Instability (NBTI) (Mandal and others, 2024; Pravadelli, 2023). When edge AI devices fail prematurely due to thermal degradation, they are discarded, directly contributing to the global electronic waste (e-waste) crisis—one of the fastest-growing waste streams worldwide. Therefore, enhancing the Mean Time To Failure (MTTF) of VLSI systems is not merely a reliability engineering goal; it is a fundamental sustainability metric. By actively managing the thermal envelope through precision scaling, Eco-SoC defers hardware replacement cycles, significantly reducing the annualized embodied carbon footprint of the deployed infrastructure. 3. Hardware Architecture: Eco-SoC Microarchitecture To achieve true energy-proportionality, the Eco-SoC architecture shifts the paradigm of approximate computing from software-level algorithmic quantization to hardware-level dynamic switching mitigation. The core philosophy is to aggressively minimize the toggling of internal capacitive nodes within the datapath whenever high-precision arithmetic is mathematically redundant. On-Chip SRAM Buffer (Activations & Weights)Leading Zero Detector (LZD)Ring Oscillator Thermal Sensor (TjT_j)DPSL Controller (FSM)TAPG Controller (Thermal Throttle)Systolic MAC Array (Clock Gated)MAC 0(INT4/8)MAC 1(INT4/8)MAC 2(INT4/8)MAC 3(INT4/8)Activation StreamSparsity FlagFreq ∝Tj T_jOverrideClock Enable (ENhighEN_high, ENlowEN_low) routed to ICG Cells Figure 1. Eco-SoC Microarchitecture. The DPSL monitors activation sparsity via Leading Zero Detectors (LZD), while the TAPG overrides precision scaling to maintain safe thermal envelopes, selectively clock-gating the Systolic MAC array. 3.1. Mathematical Power Optimization Strategy The total power consumption of a CMOS-based VLSI system is the sum of its dynamic and static (leakage) power components: (1) Ptotal=Pdyn+Pstat=(α⋅Ceff⋅Vdd2⋅f)+(Vdd⋅Ileak)P_total=P_dyn+P_stat=(α· C_eff· V_d^2· f)+(V_d· I_leak) where α is the switching activity factor (the probability of a node transitioning from 0→10→ 1 or 1→01→ 0), CeffC_eff is the effective switched capacitance, VddV_d is the supply voltage, f is the clock frequency, and IleakI_leak represents sub-threshold and gate-oxide leakage currents. While traditional low-power techniques like Dynamic Voltage and Frequency Scaling (DVFS) aggressively target VddV_d and f, DVFS suffers from high latency penalties during voltage transitions and is often too coarse-grained for the microsecond-level fluctuations of AI inferencing. Eco-SoC, instead, directly targets the switching activity factor (α) and the effective capacitance (CeffC_eff) at the clock-tree level through a novel technique we define as Dynamic Precision-Scaling Logic (DPSL). 3.2. Dynamic Precision-Scaling Logic (DPSL) The primary computational engine of Eco-SoC is a highly parallelized 2D systolic array of Multiplier-Accumulators (MACs), natively designed for INT8 precision. In standard AI accelerators, processing an activation that requires only 4 bits of precision still results in the clocking of all 8-bit registers and the full combinational toggling of the 8-bit multiplier tree, resulting in massive parasitic power waste. Eco-SoC introduces the DPSL controller, a lightweight Finite State Machine (FSM) integrated directly into the dispatch queue of the systolic array. The DPSL executes a two-stage pipeline: (1) Sparsity Detection: During the memory fetch cycle, leading zero detectors (LZDs) rapidly profile the incoming activation tensor map. If a contiguous block of activations can be mathematically represented in INT4 without overflowing, a scale_down flag is asserted. (2) Granular Clock Gating: The scale_down flag triggers Integrated Clock Gating (ICG) cells specifically attached to the upper four bits of the operands in the MAC units. By de-asserting the clock enable (EN) signal for these specific flip-flops, the DPSL physically prevents the inputs from toggling. Because the combinational logic of the multiplier tree is decoupled from transitioning inputs, the switching activity (α) for the gated paths drops to absolute zero. Our RTL synthesis confirms that while the DPSL controller introduces a 4.8% area overhead for the LZDs and control routing, it successfully reduces the aggregate dynamic power of the systolic array by 42% under standard sparse AI workloads (e.g., pruned ResNet-50 models). Algorithm 1 Eco-SoC: Hardware-Managed DPSL and TAPG Execution 0: Activation Vector A, Weight Matrix W, Junction Temp TjT_j 0: Clock Enable Signals for MAC Registers (ENhighEN_high, ENlowEN_low) 1: Initialize: Tthresh←65∘CT_thresh← 65 C, Mode←INT8Mode← INT8 2: loop 3: Tj←Read_Ring_Oscillator_Frequency()T_j \_Ring\_Oscillator\_Frequency() 4: if Tj≥TthreshT_j≥ T_thresh then 5: Mode←INT4Mode← INT4 Thermal override triggered 6: Assert Thermal_Throttle_Interrupt 7: else 8: Zeros←Leading_Zero_Detect(A)Zeros \_Zero\_Detect(A) 9: if Zeros≥4Zeros≥ 4 and Max(W)<16Max(W)<16 then 10: Mode←INT4Mode← INT4 Activation sparsity detected 11: else 12: Mode←INT8Mode← INT8 13: end if 14: end if 15: Execute Clock Gating: 16: if Mode==INT4Mode==INT4 then 17: ENhigh←0EN_high← 0 Gate upper 4 bits of MAC 18: ENlow←1EN_low← 1 19: αupper←0 _upper← 0 Switching activity neutralized 20: else 21: ENhigh←1EN_high← 1 22: ENlow←1EN_low← 1 23: end if 24: Execute_Systolic_MAC(Aactive,Wactive)Execute\_Systolic\_MAC(A_active,W_active) 25: end loop 3.3. Hardware-Managed Thermal-Aware Power Gating (TAPG) Aggressive dynamic power reduction not only saves energy but directly modulates the thermal density of the silicon. To maximize device longevity and prevent the thermal runaway common in FinFET nodes, Eco-SoC implements a hardware-managed Thermal-Aware Power Gating (TAPG) loop. We distribute lightweight Ring Oscillator (RO) based thermal sensors across the die, adjacent to the most computationally dense MAC clusters. The frequency of an RO is highly sensitive to the localized junction temperature (TjT_j). The TAPG controller continuously monitors the RO frequencies. If TjT_j approaches a predefined sustainability threshold (e.g., 65∘65 C), the TAPG overrides the software-defined precision requirements and forces the DPSL to scale down to INT4 or INT2 precision. By actively throttling precision in hardware—rather than relying on slow, OS-level DVFS interrupts—Eco-SoC instantly reduces the localized power density, allowing the silicon to cool. This mechanism guarantees that the SoC strictly adheres to a long-term thermal envelope, directly contributing to the exponential increase in the Mean Time To Failure (MTTF) modeled in Section 4. 4. Sustainability Modeling and Life Cycle Assessment (LCA) While the Dynamic Precision-Scaling Logic (DPSL) significantly optimizes operational energy, a true evaluation of VLSI sustainability must encompass the entire device lifecycle. To quantify the environmental efficacy of Eco-SoC, we utilize a cradle-to-grave Life Cycle Assessment (LCA) methodology, heavily informed by the Architectural Carbon footprint Tool (ACT) framework (Gupta and others, 2024). We define the total environmental impact (in kgCO2ekgCO_2e) of an edge-deployed System-on-Chip as: (2) Impactotal=Cfab+∑t=0Life(Pops(t)×CI(t))+EwasteImpact_total=C_fab+ _t=0^Life (P_ops(t)× CI(t) )+E_waste where CfabC_fab represents the embodied carbon generated during the mining, wafer fabrication, and packaging phases; Pops(t)P_ops(t) is the dynamic operational power consumed at time t; CI(t)CI(t) is the Carbon Intensity of the local electrical grid (measured in gCO2e/kWhgCO_2e/kWh); and EwasteE_waste represents the end-of-life environmental penalty of electronic waste disposal. 4.1. The Carbon Payback Period for Silicon Area Advanced sub-10nm fabrication nodes (such as the 7nm FinFET process used for our synthesis) are highly carbon-intensive due to the prolonged usage of Extreme Ultraviolet (EUV) lithography and complex multi-patterning steps. As detailed in Section 3, the integration of DPSL control logic and thermal sensors introduces a 4.8% increase in silicon die area. Under traditional PPA paradigms, this area bloat would be viewed as a pure penalty. However, under the ACT framework, area increases are modeled as a localized increase in embodied carbon (ΔCfab C_fab). For the architecture to be classified as ”sustainable,” the operational energy savings (ΔPops P_ops) must amortize this initial carbon debt within the expected lifetime of the device. We define the Carbon Payback Period (TpaybackT_payback) as the time required to achieve net-zero environmental impact relative to a baseline, static SoC: (3) Tpayback=ΔCfab(ΔPops×CIgrid)×DutyCycleT_payback= C_fab ( P_ops× CI_grid )× DutyCycle Assuming a global average grid carbon intensity (CIgridCI_grid) of 475 gCO2e/kWh475 gCO_2e/kWh and an active inferencing duty cycle of 20% for a standard edge-AI camera deployment, the 42% reduction in dynamic power provided by the DPSL generates massive operational carbon savings. Our LCA calculations demonstrate that Eco-SoC offsets its 4.8% area carbon penalty in just T≈14T≈ 14 months (1.1 years). Because the standard lifespan of consumer edge devices is 3 to 5 years, Eco-SoC provides a net-negative carbon delta for the majority of its deployment. 4.2. Reliability as Sustainability: The E-Waste Mitigation Model The most direct method to reduce both embodied carbon (CfabC_fab) and physical e-waste is to maximize the physical longevity of the silicon. As established in Section 3.3, Eco-SoC utilizes Thermal-Aware Power Gating (TAPG) to maintain strict junction temperatures (Tj≤65∘T_j≤ 65 C). To mathematically quantify the sustainability benefit of this thermal management, we model the Mean Time To Failure (MTTF) of the interconnects and gate oxides using the established Arrhenius relationship: (4) MTTF=A⋅exp(EakB⋅Tj)MTTF=A· ( E_ak_B· T_j ) where A is an empirical scaling constant dependent on the 7nm process geometry, EaE_a is the activation energy of the primary failure mechanism (e.g., 0.7 eV0.7 eV for Electromigration), kBk_B is the Boltzmann constant (8.617×10−5 eV/K8.617× 10^-5 eV/K), and TjT_j is the absolute junction temperature in Kelvin. In a baseline SoC without dynamic precision scaling, sustained intensive AI workloads frequently push TjT_j to 85∘85 C (358 K358 K). By actively throttling power density and maintaining a maximum TjT_j of 65∘65 C (338 K338 K), Eco-SoC fundamentally alters the exponential decay curve of the silicon. Evaluating the Arrhenius equation yields: (5) MTTFEcoMTTFBase=exp[0.78.617×10−5(1338−1358)]≈2.02 MTTF_EcoMTTF_Base= [ 0.78.617× 10^-5 ( 1338- 1358 ) ]≈ 2.02 By keeping the silicon cooler, Eco-SoC effectively doubles (a 102.3% increase) the projected hardware lifespan from 4.2 years to 8.5 years. By deferring the replacement cycle, the annualized embodied carbon footprint of the edge device fleet is cut in half, representing a massive mitigation of global electronic waste. 5. Experimental Evaluation and EDA Synthesis To validate the area, power, and timing (APT) impacts of the Dynamic Precision-Scaling Logic (DPSL) and the Thermal-Aware Power Gating (TAPG) mechanisms, we implemented the Eco-SoC architecture at the Register-Transfer Level (RTL) using SystemVerilog. 5.1. Methodology and EDA Toolchain The baseline architecture and the proposed Eco-SoC were synthesized using the Synopsys Design Compiler. We targeted a predictive 7nm FinFET standard cell library characterized at a nominal supply voltage of 0.7V0.7V and a standard operating temperature of 25∘25 C. To accurately capture the dynamic switching activity (α), we simulated the post-synthesis netlist using Mentor Graphics ModelSim. We drove the simulation with real-world activation maps extracted from quantized and pruned ResNet-50 and MobileNetV2 models processing the ImageNet dataset. The resulting Value Change Dump (VCD) files were fed into Synopsys PrimeTime PX for high-fidelity vector-driven power analysis. 5.2. Area, Power, and Timing (APT) Analysis The integration of the DPSL finite state machines, leading zero detectors (LZDs), and the distributed Ring Oscillator thermal sensors inherently introduces hardware overhead. Our synthesis results, detailed in Table 1, indicate that Eco-SoC requires a total die area of 1.31 m21.31 m^2 for the accelerator core, representing a marginal 4.8% area penalty compared to the statically wired baseline (1.25 m21.25 m^2). Furthermore, the insertion of Integrated Clock Gating (ICG) cells in the data paths introduces a slight setup-time penalty. However, by leveraging the fast switching characteristics of the 7nm FinFET node, Eco-SoC maintains the target clock frequency of 1.2 GHz1.2 GHz without violating critical path timing constraints. Table 1. APT and Sustainability Metrics Synthesis (7nm FinFET, 1.2 GHz, 0.7V) Evaluation Metric Baseline Static SoC Eco-SoC (DPSL + TAPG) Relative Improvement Dynamic Power (PdynP_dyn) 450.2 mW 261.1 mW 42.0% Reduction Static Leakage (PstatP_stat) 42.5 mW 44.8 mW -5.4% (Penalty) Total Die Area 1.25 m21.25 m^2 1.31 m21.31 m^2 -4.8% (Penalty) Target Clock Frequency 1.2 GHz 1.2 GHz 0.0% (Maintained) Energy-Delay Product (EDP) 1.00× (Normalized) 0.62× 38.0% Improvement Carbon Payback Period N/A (Net Positive) 1.1 Years Offset Achieved Mean Time To Failure (MTTF) 4.2 Years 8.5 Years 102.3% Extension As demonstrated in Table 1, the 42% reduction in dynamic power overwhelmingly compensates for the 5.4% increase in static leakage caused by the additional DPSL logic gates. The overarching Energy-Delay Product (EDP), a critical metric for evaluating hardware efficiency, improves by 38% across standard inference workloads. 5.3. Workload-Specific Power Profiling To prove the dynamic adaptability of the Eco-SoC architecture, we profiled the dynamic power consumption across three distinct Convolutional Neural Network (CNN) topologies: ResNet-50, MobileNetV2, and VGG-16. Because the Dynamic Precision-Scaling Logic (DPSL) relies on activation sparsity, models utilizing aggressive ReLU (Rectified Linear Unit) activation functions inherently trigger deeper clock-gating. ResNet-50MobileNetV2VGG-160200200400400600600450450310310520520261261165165380380Dynamic Power (mW)Baseline Static SoCEco-SoC (DPSL Active) Figure 2. Dynamic power consumption across standard vision workloads. MobileNetV2 exhibits the highest relative power savings (46.7%) due to its highly sparse depthwise separable convolutions, which the DPSL efficiently down-scales to INT4. As illustrated in Figure 2, MobileNetV2 achieves the highest relative power savings. Its reliance on depthwise separable convolutions generates highly sparse activation maps, allowing the DPSL controller to aggressively clamp the upper 4 bits of the MAC registers for over 70% of the inference cycle. 6. Conclusion The era of optimizing VLSI architectures strictly for peak performance without regard for environmental impact is no longer tenable. As edge AI deployments scale globally, the semiconductor industry must address both operational energy consumption and the massive embodied carbon footprint of sub-10nm fabrication. This paper introduces Eco-SoC, an architecture co-designed for sustainable artificial intelligence. By shifting from static execution to dynamic energy-proportionality, our hardware-level Dynamic Precision-Scaling Logic (DPSL) mitigates unnecessary switching capacitance, reducing operational dynamic power by 42%. Through a rigorous Life Cycle Assessment (LCA) utilizing the ACT framework, we mathematically prove that these operational savings completely offset the embodied carbon of the 4.8% silicon area overhead within just 1.1 years. Finally, by managing the thermal envelope in real-time, Eco-SoC doubles the physical lifespan of the silicon, providing a highly scalable, immediate solution for reducing global electronic waste. Acknowledgements.The authors disclose that generative AI models were utilized during the preparation of this manuscript to assist with LaTeX formatting, bibliography structuring, and technical prose refinement. The final architectural designs, mathematical models, and technical conclusions remain the sole intellectual responsibility of the human authors. References J. Albericio et al. (2016) Cnvlutin: ineffectual-neuron-free deep neural network computing. In ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), p. 1–13. Cited by: §2.2. L. A. Barroso and U. Hölzle (2007) The case for energy-proportional computing. Computer 40 (12), p. 33–37. Cited by: §1. H. Esmaeilzadeh et al. (2011) Dark silicon and the end of multicore scaling. IEEE Micro 32 (3), p. 122–134. Cited by: §2. V. Grimblatt et al. (2024) Sustainable design methodologies for next-generation socs. ACM Journal on Emerging Technologies in Computing Systems (JETC) 20. Cited by: §1, §2.1. U. Gupta et al. (2024) ACT: designing sustainable computer architecture. In International Symposium on Computer Architecture (ISCA), Cited by: §1, §2.1, §4. J. L. Hennessy and D. A. Patterson (2023) A new golden age for computer architecture: domain-specific hardware/software co-design. Communications of the ACM. Cited by: §1. ITRS Committee (2025) Semiconductor sustainability roadmap 2030. In IEEE International Electron Devices Meeting (IEDM), Cited by: §2.1. N. P. Jouppi et al. (2017) In-datacenter performance analysis of a tensor processing unit. In Proceedings of the 44th annual international symposium on computer architecture, p. 1–12. Cited by: §2.2. S. Mandal et al. (2024) Thermal-aware resource management in multicore socs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Cited by: §1, §2.3. G. Pravadelli (2023) Advanced verification and testing for sustainable vlsi systems. Springer Nature. Cited by: §1, §2.3. L. Wang et al. (2025) Approximate computing for green ai: a survey of hardware trade-offs. In Design Automation Conference (DAC), Cited by: §1, §2.2.