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AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewriting
Yiting Wang, Chenhui Deng, Chia-Tung Ho, Yanqing Zhang, Zhuo Feng, Cunxi Yu, Ang Li, Gang Qu, Brucek Khailany
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Summary
AUTOGATE is an agentic framework designed for automated, workload-aware fine-grain clock gating (FGCG) optimization in large-scale, hierarchical RTL codebases. It addresses the limitations of current LLM-based RTL optimization—specifically the inability to process long waveform traces and the difficulty of scaling to complex hierarchies—by using an ML-LLM co-design. The framework employs an ML-based clustering algorithm to distill raw toggling traces into compact, structured representations (stability patterns) that guide LLM agents. It utilizes a hierarchical multi-agent architecture with an orchestrator and specialized sub-agents to perform bottom-up, module-level RTL rewriting. Experimental results show significant dynamic power reductions across various designs, including NVDLA and BlackParrot, while maintaining minimal area overhead.
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AUTOGATE → implements → multi-agent architecture
confidence 100% · To enhance scalability, AUTOGATE employs a hierarchical multi-agent architecture that decomposes large designs into independently optimizable modules
AUTOGATE → optimizes → NVDLA
confidence 100% · On industry-scale designs, it achieves 19.34% and 7.96% dynamic power reductions on NVDLA and BlackParrot, respectively
ML-based clustering algorithm → processes → toggling traces
confidence 100% · Specifically, we design an ML-based clustering algorithm that distills raw toggling traces into compact, structured representations
AUTOGATE → uses → ML-based clustering algorithm
confidence 100% · Specifically, we design an ML-based clustering algorithm that distills raw toggling traces into compact, structured representations that guide LLM-based RTL rewriting.
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Abstract
Abstract:Fine-grain clock gating (FGCG) is among the most effective techniques for reducing dynamic power, yet current FGCG optimization flows remain largely manual. Recent LLM-based RTL optimization approaches remain limited by two key drawbacks: (1) the inability to process long waveform traces spanning millions of cycles, and (2) the difficulty of scaling optimization to large hierarchical codebases while preserving correctness. In this work, we present AUTOGATE, the first agentic framework for industry-grade RTL power optimization, enabling workload-aware clock-gating optimization across large hierarchical codebases. AUTOGATE introduces a Machine Learning (ML)-LLM co-design that bridges waveform-level analysis and RTL rewriting. Specifically, we design an ML-based clustering algorithm that distills raw toggling traces into compact, structured representations that guide LLM-based RTL rewriting. This enables accurate identification and application of clock-gating opportunities without requiring LLMs to directly process raw waveform data. To enhance scalability, AUTOGATE employs a hierarchical multi-agent architecture that decomposes large designs into independently optimizable modules, enabling coordinated optimization across deep design hierarchies. We evaluate AUTOGATE on a diverse set of designs ranging from small RTL designs to large industrial-grade codebases. Experimental results show that AUTOGATE consistently reduces dynamic power relative to baselines. Across the small-design suite, AUTOGATE reduces dynamic power by 49.31% on average. On industry-scale designs, it achieves 19.34% and 7.96% dynamic power reductions on NVDLA and BlackParrot, respectively, and up to 6.86% on highly optimized proprietary production designs.
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- Source: https://arxiv.org/abs/2606.17461v1
- Canonical: https://arxiv.org/abs/2606.17461v1
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AUTOGATE: Automated Clock Gating via Toggling-Aware LLM-based RTL Rewriting Yiting Wang ∗† , Chenhui Deng ‡ , Chia-Tung Ho ‡ , Yanqing Zhang ‡ , Zhuo Feng ‡ , Cunxi Yu †‡ , Ang Li † , Gang Qu † , Brucek Khailany ‡ † University of Maryland, College Park, ‡ NVIDIA ywang144, angliece, gangqu@umd.edu, cdeng, chiatungh, yanqingz, zhuof, cunxiy, bkhailany@nvidia.com Abstract—Fine-grain clock gating (FGCG) is among the most effective techniques for reducing dynamic power, yet current FGCG optimization flows remain largely manual. Recent LLM- based RTL optimization approaches remain limited by two key drawbacks: (1) the inability to process long waveform traces spanning millions of cycles, and (2) the difficulty of scaling optimization to large hierarchical codebases while preserving correctness. In this work, we present AUTOGATE, the first agentic framework for industry-grade RTL power optimiza- tion, enabling workload-aware clock-gating optimization across large hierarchical codebases. AUTOGATE introduces a Machine Learning (ML)–LLM co-design that bridges waveform-level analysis and RTL rewriting. Specifically, we design an ML- based clustering algorithm that distills raw toggling traces into compact, structured representations that guide LLM-based RTL rewriting. This enables accurate identification and application of clock-gating opportunities without requiring LLMs to directly process raw waveform data. To enhance scalability, AUTOGATE employs a hierarchical multi-agent architecture that decomposes large designs into independently optimizable modules, enabling coordinated optimization across deep design hierarchies. We evaluate AUTOGATE on a diverse set of designs ranging from small RTL designs to large industrial-grade codebases. Experimental results show that AUTOGATE consistently reduces dynamic power relative to baselines. Across the small-design suite, AUTOGATE reduces dynamic power by 49.31% on average. On industry-scale designs, it achieves 19.34% and 7.96% dynamic power reductions on NVDLA [1] and BlackParrot [2], respectively, and up to 6.86% on highly optimized proprietary production designs. Index Terms—RTL power optimization, clock gating, large language models, agentic framework I. INTRODUCTION Power consumption is a first-order design constraint in modern very-large-scale integration (VLSI) systems on a chip. Dynamic power is driven by switching on clock networks, data paths, and interconnects. Fine-grain clock gating (FGCG) gates small groups of flip-flops to reduce dynamic power consumption [3]. Today’s commercial synthesis tools support automatic clock-gating inference at the register transfer level (RTL) by exploiting clock-gating opportunities that are explic- itly exposed by the RTL coding style. Consequently, many workload-dependent FGCG opportunities cannot be discovered by these synthesis tools before RTL restructuring. Such RTL rewriting is overwhelmingly manual, driven by rigid heuristics ∗ This work was conducted during an internship at NVIDIA. and the design team’s experience. Workload-aware automated FGCG optimization remains largely unexplored. Recent large language models (LLMs) have demonstrated strong capabilities in RTL code understanding, generation, and optimization [4]–[9], making LLMs promising candidates for automated RTL rewriting to improve FGCG. However, their practical adoption is restricted by the following two limitations. First, FGCG requires the analysis of long waveform that exceeds the capabilities of current LLMs. Effective FGCG relies on cycle-accurate toggling behavior that is tightly coupled with input stimuli and workload characteristics, requiring analysis of waveform traces spanning millions of clock cycles. Such traces translate into extremely long contexts, far beyond what LLMs can process accurately and reliably, making it difficult to reason and discover the patterns that might lead to dynamic power bottlenecks. Consequently, raw waveform data must first be analyzed and summarized into compact representations before it can be processed in any LLM- based flow. Meanwhile, FGCG clustering algorithms, from coarse toggle-rate-based grouping to sequence-level clustering methods [10]–[12], can identify candidate flip-flop groups, but rewriting/translating these into correct and efficient RTL is challenging because of the need for deep RTL understanding and careful handling of control and data dependencies. This raises an open question: how can LLM-based RTL optimization be effectively integrated with specialized Machine-Learning (ML)-driven waveform analysis to enable accurate clock-gating decisions without requiring LLMs to directly process raw switching traces? Second, existing LLM-based RTL optimization ap- proaches do not scale to large and hierarchical industrial- grade designs. Prior LLM-based RTL optimization studies [7]– [9] have primarily focused on small, single-module designs with only a few hundred lines of code, whereas industrial designs consist of deeply hierarchical codebases with many interacting modules and complex cross-module dependencies, as demon- strated in Table I. In such settings, a single-agent, single-context approach does not scale, as effective optimization requires coordinated reasoning across the entire design hierarchy. The challenge is further compounded by large SoC designs typically providing only top-level testbenches. Because FGCG relies on module-level switching activity, practical optimization must also obtain module-level behavior from full-design simulations. arXiv:2606.17461v1 [cs.AR] 16 Jun 2026 Table I. Motivational comparison of small and large RTL designs. Values show dynamic-power change relative to baseline. Design# FilesPOET [9]ROVER [13]AUTOGATE booth_mult1 ↓ −85.52% ↓ −79.72% ↓ −86.21% NVDLA total135+0.09%−0.01% ↓ −19.34% Our Approach. We present AUTOGATE, a workload-aware power optimization framework for industrial-scale RTL code- bases through hierarchical decomposition, activity-guided opti- mization, formal verification, and automated FGCG rewriting. AUTOGATE rewrites RTL to expose additional gating opportu- nities, enabling synthesis to infer more effective clock gating. AUTOGATE addresses the limitations of LLMs in pro- cessing long waveform traces through an adaptive switching- activity analysis. Specifically, we transform raw simulation traces into a hierarchy of clock-gating candidates using toggle- aware pre-filtering, automatic threshold discovery, and multi- threshold stability clustering. The resulting gating candidates are then distilled into a compact, structured representation that guides LLM-based rewriting, enabling the LLM to expose identified clock-gating opportunities while preserving control and data dependencies, thereby bridging waveform-level activ- ity analysis and RTL optimization. Notably, when improving gating efficiency, the LLM may merge existing clock gates in the original design. As a result, area reduction may occur as a byproduct of clock-gate merging. To scale up to industrial-grade RTL codebases, AUTO- GATE uses a divide-and-conquer strategy that decomposes complex hierarchical designs into independently optimizable modules, enabling scalable and coordinated optimization across the entire design. We use a multi-agent architecture in which an orchestrator LLM automatically identifies the design hierarchy, partitions the codebase into manageable units, and leverages per- module switching activity analysis to guide optimization. This approach enables AUTOGATE to scale effectively to production- level designs while preserving cross-module correctness and optimization consistency. We conduct extensive experiments on 10 designs, spanning small single modules, industrial-grade designs, and highly opti- mized proprietary production designs. Our results demonstrate that AutoGate consistently outperforms competitive baselines in terms of dynamic power reduction. Our contributions are as follows: 1)We propose AUTOGATE, the first agentic framework for industrial-grade RTL power optimization, enabling workload-aware FGCG across large hierarchical codebases. 2)We address the limitations of LLMs in precisely under- standing long-context waveforms by co-designing an ML- based toggling analysis method to guide LLM decisions. This combines the strengths of ML-based long sequence processing and LLM-based RTL reasoning to improve FGCG effectiveness. 3)We demonstrate that AUTOGATE exposes clock-gating opportunities beyond those identified by a commercial synthesis flow with aggressive automatic clock-gating inference enabled. Across small benchmarks, AUTOGATE achieves an average dynamic-power reduction of 49.31% with only 0.15% average area overhead. 4)We overcome the scalability limitations of LLM-based RTL optimization through divide-and-conquer optimiza- tion of large hierarchical codebases with complex cross- module dependencies. On large industrial-grade designs, AUTOGATE achieves average dynamic-power reductions of 19.34% on NVDLA with a 3.46% average area reduction across partitions, 7.96% on BlackParrot with 0.04% area overhead, and up to 6.86% on highly optimized proprietary production designs with at most 1% area overhead. I. BACKGROUND A. Dynamic Power and Clock Gating Dynamic power is a dominant component of power con- sumption in modern digital designs. It is commonly modeled as P dyn = α· C L · V 2 D · f clk , whereαis the switching activity factor,C L is the load capacitance,V D is the supply voltage, andf clk is the clock frequency. At the RTL stage, the supply voltage, technology capacitance, and target clock frequency are usually fixed by design constraints. Therefore, reducing unnecessary switching activity is one of the most effective methods for dynamic power optimization. Fine-grain clock gating (FGCG) reduces unnecessary switch- ing by inserting integrated clock-gating (ICG) cells to small groups of flip-flops. When the registers in a group do not need to update, the ICG suppresses the clock, reducing switching in both the clock path and the flip-flops. However, FGCG is not free: each additional ICG introduces area, control logic, and clock-tree overhead. Effective FGCG therefore requires selecting register groups whose idle cycles align well enough to justify the added gating logic. B. RTL Coding Style of inserting FGCG In standard digital design flows, logic synthesis tools infer FGCG from RTL coding patterns rather than from manually instantiated ICG cells. Fig. 1 compares two common coding styles: the right style exposes an explicit hold condition, while the left style assigns the register on every cycle. In Fig. 1(a),qis assigned every cycle and therefore does not expose a clock-gating opportunity. In contrast, the explicit hold condition in Fig. 1(b) enables synthesis to infer a clock gate, whose hardware implementation is shown in Fig. 1(c). FGCG-oriented RTL rewriting therefore transforms functionally equivalent code into forms that expose register hold behavior and enable clock-gating inference. C. Related Work Recent LLM-based hardware design methods have demon- strated promising capabilities in Verilog generation [4], [5], chip design assistance [6], and RTL optimization through LLM-guided rewriting [8], e-graph rewriting [14], symbolic reasoning [7], and evolutionary search [9]. However, existing methods neither address the workload-dependent nature of CG not inserted always @(posedge clk) begin if (condition_a) q <= data_a; else q <= data_b; end (a) CG inserted always @(posedge clk) begin if (enable) q <= d; // else: hold q end (b) ICG enable clk gated clk d DQ q (c) Fig. 1. RTL coding styles for synthesis-inferred FGCG and the corresponding gated-register schematic. Table I. Comparison of LLM-based RTL optimization methods. Power Aware indicates explicit power optimization, Clock Gating indicates support for clock-gating transformations, Agent Based indicates an agentic workflow, Repo Level indicates support for large, multi-file RTL codebases, and Custom Algo. indicates custom algorithm-guided rewriting. Method Power Aware Clock Gating Agent Based Repo Level Custom Algo. RTLRewriter [8]✓✗✓✗ ROVER [13]✓✗✓ SymRTLO [7]✓✗✓✗✓ ASPEN [14]✗✓✗✓ POET [9]✓✗✓✗ AUTOGATE (Ours)✓ automated FGCG nor provide a scalable solution for industrial- scale RTL repositories. First, FGCG is workload-dependent and requires processing cycle-level switching activity, while realistic traces can span millions of cycles and exceed practical LLM context limits. Second, most RTL optimization methods target small or single-module designs and do not scale to hierarchical industrial-grade RTL codebases with cross-module dependencies. Non-LLM approaches face similar limitations: rule-based methods [13] rely on predefined rewrite patterns with limited generalization capability, while clustering-based flows [10]–[12] require manual tuning and expert interpretation to translate clustering results into effective RTL rewrites. These limitations motivate a framework that combines workload- aware FGCG analysis with hierarchy-aware LLM-based RTL rewriting. Table I compares the capabilities of existing RTL optimization frameworks with AUTOGATE. D. Motivational Experiment To demonstrate the limitations in existing RTL optimization methods in hierarchical RTL codebases, we have performed a motivational experiment. Table I shows this gap using one single-module benchmark and one large RTL design. On the single module booth multiplier design, both LLM- based method (POET [9]) and non LLM-based method (ROVER [13]) significantly reduce dynamic power. However, when the dynamic power of the reported NVDLA partitions is aggregated under the same workload, both methods provide nearly no improvement. This motivates a scalable, hierarchy- aware optimization flow for large hierarchical RTL codebases. I. METHODOLOGY AUTOGATE framework consists of four stages as shown in Fig. 2, and we will elaborate each of them next. A. Stage 1: Hierarchy Detection and Pre-Profiling Large RTL codebases typically exhibit deep and complex design hierarchies with massive code volume, often exceeding the context window of LLMs and making holistic understanding impractical. Furthermore, synthesizing and performing power analysis on the entire codebase is computationally expensive, often requiring hours to days, which makes iterative opti- mization with power feedback very challenging at the full- design level. To address these challenges, AUTOGATE adopts a divide-and-conquer strategy that decomposes the design into modules, identifies power-critical components, and applies targeted optimization to each module independently, as shown in Fig. 2 Stage 1 ⃝ . AUTOGATE begins by constructing an explicit design hier- archy from the RTL source tree, where the orchestrator parses module definitions and instantiations to resolve parent–child relationships and identify independently optimizable modules. It then traverses this hierarchy using depth-first search to perform per-module pre-profiling, recording structural features such as module paths, sequential logic regions, and register counts. To incorporate power information, AUTOGATE maps synthe- sized gate-level instances back to their originating RTL files and source lines, and aggregates gate-level power estimates by RTL region and logic category. This is combined with synthesis and power metrics, including total and dynamic power, clock-gating coverage and efficiency, flop count, and ICG count. The resulting structured power bottleneck report ranks modules by optimization value and captures source-level power attribution, clock-gating headroom, and downstream impact, allowing AUTOGATE to focus only on promising candidates and avoid unnecessary rewriting. By following this divide-and- conquer strategy, AUTOGATE requires full-design synthesis and power analysis only once. FGCG analysis is a key component of clock-gating can- didate selection and requires per-module switching traces. However, large RTL projects typically provide only top-level or subsystem-level testbenches, and manually writing standalone testbenches for every internal module would undermine au- tomation. AUTOGATE addresses this by extracting module-level testbenches directly from full-design simulation traces for each bottleneck module. It parses module interfaces, extracts scoped waveform data, and generates standalone testbenches that replay real workload inputs cycle by cycle. This enables accurate per- module switching analysis while preserving realistic system behavior, avoiding reliance on synthetic stimuli. B. Stage 2: Adaptive Stability-Based FGCG Exploration Unlike prior FGCG methods that produce a single clustering result, AUTOGATE generates a hierarchy of candidate clus- terings spanning different power-area tradeoffs. As shown in Fig. 2 Stage 2 ⃝ and detailed in Fig. 3, RTL switching traces from the extracted testbench are processed through four steps: Fig. 2. AUTOGATE framework overview. 1 ⃝ identifies optimization targets and extracts module-level workloads; 2 ⃝ generates FGCG candidates from switching activity; 3 ⃝ performs parallel LLM-guided RTL rewriting; and 4 ⃝ verifies and selects QoR-improving candidates. 1 Signal Pre-Filter Counter32 (Standard) always@(posedgeclk) begin if(reset) begin counter <= 32'b0; endelseif(enable) begin counter <= counter + 32'd1; end end LOW (Low Activity) One Gating Group 2 Automatic Clustering Threshold Discovery 4-bit wiseStability Matrix 3 Stability-Based Clustering Signal Switching Activity Clu sters Clu ster 1 bits [0:3] (First 4 bits) Clu ster 2 bits [4:31] (Last 28 bits) 4 Structured Report+ RTL opt HIGH (High Activity) No Gating Needed MID (Mid Activity) Counter32 (Gated) always@(posedgeclk) begin if(reset) counter_low<= 4'b0; elseif(enable) counter_low<= counter_low+ 4'd1; end always@(posedgeclk) begin if(reset) counter_hi<= 28'b0; elseif(enable && (counter_low== 4'hF)) counter_hi<= counter_hi+ 28'd1; end Group 2: bits: [4, 5, 6, ..., 31] Q/ CLK: 0. 4-3.1% Effic ie ncy: 96.9% Group 1: bits: [0, 1, 2, 3] Q/ CLK: 6. 2-49.9% Effic ie ncy: 50.0% Signal Stability Pattern Coarse-Grained Clu sterin g On Q/CLK Ratio LLM Agent Analyze Fig. 3. Adaptive Stability FGCG clustering flow. 1 toggle-aware pre-filtering partitions registers into activity bands;2switching traces are converted into binary stability patterns and are then assembled into the stability matrix for automatic threshold discovery;3stability-based clustering forms candidate FGCG groups; and4structured optimization reports are generated for the LLM agents. Stability Patterns and Group Efficiency. [12] LetR = r 1 ,...,r N be the register set under analysis, andTbe the number of observed clock edges. A candidate gating groupG⊆Ris the set of registers proposed to share one inferred ICG. The stability pattern of registerais a binary sequenceSP a ∈ 0, 1 T , whereSP a [k] = 1indicates that registeraremains unchanged at clock edgek, andSP a [k] = 0otherwise. Since that ICG can be disabled only when all registers inGare stable, the group stability is the element- wise logical ANDSP G [k] = V a∈G SP a [k]. The group gating efficiencyE(G) = 1 T P T k=1 SP G [k] is therefore the fraction of cycles in which the whole group can safely gate its clock. Clustering starts from singleton groups and repeatedly merges the closest pair of current clustersC i ,C j ⊆Runder d(C i ,C j ) = ∥SP C i − SP C j ∥ 2 , accepting a merged cluster M = C i ∪ C j only when its ANDed stability vector satisfies E(M )≥ minE. 1 Toggling-aware Pre-Filter. To avoid applying unnecessary clock gating to flops with little optimization benefit, AUTOGATE first filters registers based on their toggle rates. Registers with toggle rates close to 0 or 1 are unlikely to benefit from gating and are therefore excluded. Specifically, before stability clustering, AUTOGATE partitions registers in each module into low, middle, and high toggle-rate bands using their measured Q/CLK ratio under the target workload, with thresholds of 3% and 95% for the low and high bands, respectively. Stability clustering is then applied only to the middle band to reduce computational cost and focus on the most promising candidates. If the middle band is empty, a fallback mode is triggered that includes all registers. These threshold values are fixed across all experiments; systematic tuning of these parameters is out of the scope of this work and is left for future work. 2 Automatic Threshold Selection. The stability-based FGCG clustering algorithm [12] depends on a manually chosen mini- mum group gating-efficiency thresholdminE. This threshold is fragile: too low merges unrelated registers into one gate, while too high produces single-register clusters that waste area. AUTOGATE removes this manual tuning by computing a fixed-size group-wise efficiency spectrum. For a candidate group sizeb, we setbto the minimum clock-gating bit-width. Unless otherwise specified,b = 4, matching the default setting of the commercial synthesis tool. The efficiency spectrum evaluates everyb-register candidate group:E b = E(H) | H ⊆ R, |H| = b, whereE(H) = 1 T P T k=1 min a∈H SP a [k] .Rdenotes the register set under anal- ysis. The algorithm sorts the N b group efficiencies, identifies the largest consecutive gaps, and uses the corresponding gap midpoints as candidateminEvalues. For large register sets, we sample candidate groups to identify the threshold gaps and avoid combinatorial explosion. 3Multi-Threshold Clustering. To explore the power-area trade-offs across different clustering granularity and identify the most balanced rewrite options, AUTOGATE runs the clustering algorithm at each detected group gating-efficiency threshold to generate a hierarchy of candidate FGCG assignments. The finest level creates more ICGs and maximizes gating opportunity; coarser levels reduce ICG count and area overhead. An adaptive sweep probes around each threshold with scale-proportional offsets to provide additional actionable multi-register groups, giving the LLM agents a richer set of rewrite options. 4Gating-Candidate Report. For every high-impact module, the report lists inefficient ICGs, the registers responsible for wasted toggles, recommended FGCG cluster assignments, and RTL regions where rewrites should be applied. The report is structured to be concise for LLM consumption: it names the relevant signals, ranks them by power impact, and explains the gating pattern that the rewrite should expose. C. Stage 3: LLM-Guided Parallel Rewriting To enable scalable RTL optimization, AUTOGATE adopts an agentic framework that decomposes rewriting into coordi- nated module-level transformations. Using the hierarchy and clustering reports from Stages 1 and 2, an orchestrator assigns modules to sub-agents and schedules optimization bottom-up through the design hierarchy. Leaf modules are optimized first, parent modules only after child modules optimized, and independent modules are optimized in parallel. Each module is paired with a dedicated rewrite agent that operates only on the target RTL, guided by its power- bottleneck report, gating-candidate clusters under different group gating-efficiency thresholds, and a library of clock- gating rewrite templates. These templates capture common RTL transformation patterns that expose implicit idle behavior and enable synthesis-inferred clock gating. Representative patterns include: (1) enable/hold extraction, which converts Table I. Benchmark design summary. Lines of code, cell counts, and token counts are reported for the original unoptimized RTL design. DesignFilesLinesCellsTokens Small designs counter3211710185 booth_mult181806792 divide1121757842 aes_cipher1932103,58211K deframer202431482.4K mrisc71,5162,03915K Large designs NVDLA total135103,0791,757,6391.0M |—- Partition_C4354,4991,654,571545K |—- Partition_M125,58114,97556K |—- Partition_A168,14014,91581K |—- Partition_P6434,85973,178349K BlackParrot771,071,5961,140,81430.6M unconditional assignments into conditional updates to re- veal register hold conditions (e.g., rewritingq <= d;into if (en) q <= d;); (2) value-change-based gating, which guards updates based on data changes (e.g.,if (q != d) q <= d;); (3) control-signal factoring, which lifts shared enable conditions across multiple registers to form a common gating signal; and (4) register decomposition, which splits wide registers into sub-registers with hierarchical enables to increase gating opportunities. Combined with clustering guidance, these templates enable functionally equivalent RTL rewrites that are more amenable to FGCG insertion. For each module, the agent generates fine-, medium-, and coarse-grain variants. Fine-grain variants maximize gating opportunities, medium-grain variants merge nearby clusters to reduce ICG count, and coarse-grain variants retain only the highest-efficiency groups to balance power and area. Only the target module for each rewrite agent is synthesized and evaluated for power, avoiding full-design recompilation. A reflection agent evaluates generated variants, identifies the causes of power improvements or regressions, and distills them into concise lessons stored in shared global and module-specific playbooks. Guided by both power feedback and accumulated playbook knowledge, rewrite agents iteratively refine their transformations to improve optimization quality. D. Stage 4: Formal Verification and QoR-Aware Merge AUTOGATE validates each candidate through syntax check- ing, simulation, commercial formal equivalence checking, and timing validation. Only candidates that preserve functionality and timing closure proceed to QoR evaluation. Each surviving candidate is synthesized and profiled for dynamic power, area, clock-gating metrics, and timing, yielding a QoR profile containing∆P dyn ,∆A, clock-gating coverage and efficiency, ICG count, WNS, and TNS. The final candidate is selected to maximize dynamic-power reduction under predefined area and timing constraints; otherwise, the original module is retained. Accepted patches are merged hierarchically and revalidated at the parent level. IV. EXPERIMENTAL RESULTS We evaluate AUTOGATE on six small RTL benchmarks from CVDP [15], OpenCores [16], and OpenTitan [17], two industrial-scale open-source designs from NVDLA [1] and BlackParrot [2], and two highly optimized proprietary Table IV. AUTOGATE results on small benchmark designs. “Base” denotes the original design; “POET” denotes the POET [9] result; “ROVER” denotes the ROVER [13] result; “AUTOGATE” denotes the optimized design. CG Cov = clock-gating coverage; CG Eff = clock-gating efficiency. Design Total Pwr (uW) Dyn Pwr (uW) Dyn∆ Area (um 2 ) Area∆CG CovCG EffICGs WNS (ns) Timing Pass counter32_base55.7653.23—7.63—100%22.90%10.45✓ counter32_POET52.3749.02 −7.91%7.630.00%100%30.60%10.44✓ counter32_ROVER56.7854.22+1.86%8.17+7.08%100%24.50%10.27✓ counter32_AUTOGATE26.6923.78−55.33%7.75+1.57%100%82.80%20.00✓ booth_mult_base708.90683.69—95.50—9.30%8.30%10.00✓ booth_mult_POET119.2099.00 −85.52%62.33 −34.73%99.40%86.00%60.00✓ booth_mult_ROVER169.20138.66 −79.72%95.99+0.51%98.60%88.00%50.00✓ booth_mult_AUTOGATE114.4094.30−86.21%62.11−34.96%97.00%87.00%50.00✓ divide_base672.80645.20—83.93—100%15.40%10.00✓ divide_POET671.60644.40 −0.12%83.13 −0.95%100%15.40%10.00✓ divide_ROVER699.00667.64+3.48%100.61+19.87%100%15.40%10.00✓ divide_AUTOGATE302.60265.40−58.87%103.63+23.47%96.40%81.50%310.00✓ aes_base12383.008019.00—12463.42—99.97%98.31%3610.00✓ aes_POET10791.006653.00 −17.03%12467.26+0.03%99.96%98.30%3600.00✓ aes_ROVER12418.008040.00+0.26%12462.21 −0.01%99.96%98.30%3600.00✓ aes_AUTOGATE10144.006056.00−24.48%12515.56+0.42%99.95%98.40%2890.00✓ deframer_base99.1793.85—13.57—100%49.40%60.00✓ deframer_POET88.0382.81 −11.76%13.83+1.92%100%57.00%80.00✓ deframer_ROVER97.1892.05 −1.92%13.76+1.40%100%49.40%60.00✓ deframer_AUTOGATE82.3177.29−17.65%13.77+1.47%100%55.80%70.00✓ mrisc_base729.80664.45—184.92—84.00%80.40%890.06✓ mrisc_POET726.60661.10 −0.50%185.38+0.25%84.00%80.40%890.07✓ mrisc_ROVER727.90662.49 −0.29%184.44 −0.26%84.30%80.50%900.00✓ mrisc_AUTOGATE380.80310.41−53.28%201.42+8.92%95.10%90.70%1040.06✓ 012345678910 Iteration 15 10 5 0 5 10 15 20 Change from Original (%) ACTIVE 809 regs Best R8: 74.63 uW (-17.0%) Power % Area % |P|/|A| ratio 012345678910 Iteration 50 40 30 20 10 0 10 Change from Original (%) RT_IN 314 regs Best R7: 25.44 uW (-49.6%) Power % Area % |P|/|A| ratio 02345678910 Iteration 30 20 10 0 10 20 30 40 Change from Original (%) RT_OUT 183 regs Best R8: 22.53 uW (-31.0%) Power % Area % |P|/|A| ratio 012345678910 Iteration 50 0 50 100 Change from Original (%) CFG 5 regs Best R4/R7: 0.50 uW (-89.2%) Power % Area % |P|/|A| ratio 0 20 40 60 80 100 120 140 |dPower| / |dArea| ratio inf 7.2x 0.3x inf 1.2x 151.3x 69.9x 3.2x 3.2x 3.2x 0 10 20 30 40 |dPower| / |dArea| ratio 8.0x 10.3x 5.3x 3.0x 43.3x 8.1x 5.7x 7.9x7.9x7.9x 0 2 4 6 8 10 12 |dPower| / |dArea| ratio 0.4x 1.8x 6.7x6.7x6.7x 7.6x 1.5x 11.8x 6.4x 0.0 0.2 0.4 0.6 0.8 1.0 1.2 |dPower| / |dArea| ratio 1.1x1.1x 1.0x 1.0x 1.1x 1.1x inf 0.7x 1.1x Fig. 4. Power vs. area tradeoff across the four optimized partition M sub-modules. Each point represents a candidate rewrite; the selected variants (star) achieve the best power–area balance. production designs. Table I summarizes the characteristics of the open-source designs. We compare AUTOGATE against two recent RTL power- optimization approaches, POET [9] and ROVER [13]. Since publicly available implementations are unavailable, we re- implement their approaches and evaluate them using the same synthesis, simulation, SAIF generation, PrimePower analysis, formal verification, and timing constraints as AUTOGATE. All reported power and area changes are measured relative to the original baseline RTL design. POET and ROVER have primarily been evaluated on small designs and do not provide a repository-scale optimization flow. For comparison on large designs, we apply POET and ROVER to the same modules and partitions selected by AUTOGATE’s hierarchy analysis. The resulting RTL modifications are then merged and evaluated under the same full-design workloads as AUTOGATE. Both AUTOGATE and the POET baseline use Claude Opus 4.7 with the same token budget. The POET baseline was configured with a population size ofN = 10, maximum generationsG = 10, offspringL = 10per generation, and three repair attempts per candidate. All designs were synthesized in a commercial 3 nm-class technology library using the design-specified target clock period (or 1 ns when unspecified), and use the most aggressive automatic clock-gating setting with minimum clock-gating bit- width = 4. Power was evaluated from gate-level SAIF traces and correctness was verified using commercial formal equivalence checking. These settings match the production synthesis flow used in industrial design practice. All reported savings arise solely from RTL rewrites that expose clock-gating opportunities beyond those already inferred by synthesis. A. Small Benchmark Results Table IV reports results on small benchmarks ranging from single-file datapath blocks to multi-file processor RTL under diverse baseline clock-gating conditions. Since these designs do not provide testbenches, we leverage Claude Opus 4.7 to generate the corresponding synthetic testbenches and ensure that they achieve at least 95% functional coverage with a commercial simulation tool. Key Observations. The largest savings occur in designs with limited clock-gating efficiency. For example, booth multiplier (booth_mult), AUTOGATE cuts dynamic power by 86.21% by restructuring register assignments and raising clock-gating efficiency from 8.30% to 87.00%. Counter splitting and enabling refactoring lift clock-gating efficiency from 22.90% to 82.80% for counter32 and from 15.40% to 81.50% for Table V. Combined large benchmark results. The upper portion reports NVDLA partition results under two workloads; the lower portion reports full-design BlackParrot results. Workload-dependent NVDLA columns are shown under each workload, while shared NVDLA columns are shown once. NVDLA partition results Workload 1: dc_6x8x192Workload 2: dc_35x22x54 Design Total (uW) Dyn (uW) Dyn∆ CG Eff Total (uW) Dyn (uW) Dyn∆ CG Eff Area (um 2 ) Area∆ CG Cov ICGs WNS (ns) Timing Pass Part_M_base293.6089.40—96.92%755.80547.90—69.41%653.04—99.89%1350.09✓ Part_M_POET293.6089.400.00% 96.92% 755.80 547.900.00% 69.41% 653.040.00% 99.89%135 0.09✓ Part_M_ROVER293.6089.39 −0.01% 96.92% 755.80 548.00+0.02% 69.41% 653.040.00% 99.89%135 0.00✓ Part_M_AUTOGATE230.2046.80−47.60%97.83%646.40462.50−15.60%68.89%606.77−7.10%99.87%340.06✓ Part_C_base1187.00414.80—93.12%1142.00371.10—93.93%2432.80—96.37%4970.00✓ Part_C_POET1188.00415.40+0.10% 93.12% 1142.00 371.100.00% 93.93% 2433.41+0.03% 96.37%497 0.00✓ Part_C_ROVER1188.00414.70 −0.02% 93.12% 1143.00 371.100.00% 93.93% 2433.50+0.03% 96.37%497 0.00✓ Part_C_AUTOGATE1040.00372.60−10.17%93.02%1003.00336.00−9.46%93.82%2125.25−12.64%95.73%3550.00✓ Part_A_base842.70164.70—99.24%1378.00700.40—94.38%2148.94—99.83%5100.00✓ Part_A_POET842.70164.700.00% 99.24% 1378.00 700.400.00% 94.38% 2148.08 −0.04% 99.83%510 0.00✓ Part_A_ROVER842.70164.700.00% 99.24% 1378.00 700.400.00% 94.38% 2148.940.00% 99.83%510 0.00✓ Part_A_AUTOGATE834.00114.10−30.72%99.73%1252.30462.75−33.93%95.77%2276.63+5.94%99.83%5240.00✓ Part_P_base2695.0043.52—99.73%2700.0047.15—99.73%9198.16—99.79%11900.00✓ Part_P_POET2695.0043.53+0.02% 99.73% 2700.00 47.18+0.10% 99.73% 9197.98 −0.09% 99.79% 1190 0.00✓ Part_P_ROVER2697.0043.54+0.05% 99.73% 2702.00 47.20+0.11% 99.73% 9205.38+0.08% 99.79% 1190 0.00✓ Part_P_AUTOGATE2695.0041.12−5.52%99.75%2700.0044.71−5.17%99.74%9194.29−0.04%99.79%11910.00✓ BlackParrot full-design results Design Total Pwr (uW) Dyn Pwr (uW) Dyn∆ Area (um 2 ) Area∆ CG Cov CG EffICGs WNS (ns) Timing Pass BlackParrot base72,60028,950—129,863.65—99.39%99.25%46,3980.00✓ BlackParrot POET72,60028,955 +0.02%129,876.60+0.01% 99.39% 99.25%46,3980.00✓ BlackParrot ROVER72,60028,957 +0.02%129,830.19 −0.03% 99.39% 99.25%46,3980.00✓ BlackParrot AUTOGATE70,00026,645−7.96%129,921.20+0.04%99.52%99.45%44,2910.00✓ divide. And Mini-risc(mrisc) achieves a 53.28% reduction via multi-file coordination. B. Large Benchmark Results Table V reports NVDLA partition-level results under two rep- resentative testbench workloads:dc_6x8x192(Workload 1) anddc_35x22x54(Workload 2). Optimization is performed under the Workload 1 testbench, while Workload 2 evaluates cross-workload transferability. BlackParrot results are evaluated under the Dhrystone testbench workload. a) POET and ROVER results: POET and ROVER remain close to the baseline on both NVDLA and BlackParrot, showing limited scalability to large hierarchical RTL designs. POET is constrained by long waveform traces and repository-scale codebases that exceed practical LLM context limits, while ROVER relies on predefined rewrite rules and lacks workload- aware analysis. Consequently, both achieve limited power improvements. b) AUTOGATE results: AUTOGATE overcomes these limitations through switching-aware FGCG analysis algorithm and targeted, hierarchical rewriting. On NVDLA, it reduces dynamic power across all partitions under both workloads, with the largest savings on Partition_M (Workload 1,−47.60%) and Partition_A (Workload 2,−33.93%). Partition_C shows con- sistent reductions with 12.64% area savings, while Partition_P achieves smaller savings due to already high baseline efficiency (99.73%). Improvements under Workload 2 demonstrate cross- workload transferability. On BlackParrot, AUTOGATE achieves a 7.96% dynamic power reduction with only 0.04% area overhead. Additionally, clustering-guided merging of ICGs can reduce area while improving power. C. Module-Level Analysis Table VI reports the per-module results for Partition_C under the dc_6x8x192 workload, with indentation indicating module hierarchy. Of the 43 RTL modules in Partition_C, only 7 were selected for optimization based on power-bottleneck analysis. Across these modules, AUTOGATE achieves substantial power reductions with modest area overhead, while non-critical modules are retained at baseline. Figure 4 visualizes the power–area tradeoff across the optimized Partition M submodules across iterations. Each point is a formally verified candidate, and the highlighted selections show how AUTOGATE chooses variants that reduce dynamic power while constraining area growth. Table VI. Per-module power and area results for NVDLA Partition_C. Module Dynamic Power ∆ Area ∆ Partition_C−10.17% −12.64% |—- CDMA_dc−6.19%+0.05% |—- CDMA_wt−5.65% −1.81% | |—- WT_8ATMM_fifo−9.87% −0.33% |—- CSC_sg−58.70%+1.01% | |—- SG_dat_fifo0.00% −9.96% |—- CSC_dl−31.39% −0.59% |—- CSC_wl−5.08% −0.57% D. Ablation Study Ablation I: AUTOGATE Components. To quantify the contribution of each major component, we perform an ablation study on the four NVDLA partitions under the dc_6x8x192 workload. We evaluate three ablations: (1) w/o FGCG, where the agent receives no toggle-based clustering report; (2) w/o Pre-Profile, where the agent loses power bottleneck detection and hierarchy guidance; and (3) w/o TB, where synthetic per- module testbenches replace extracted workload-driven stimuli. Fig. 5 reports the resulting dynamic-power improvements in log scale. The full AUTOGATE achieves the best results. Part. MPart. CPart. APart. P 0.1 0.5 1 5 10 50 Dyn. power improv. (%) log scale 3.2% 1.8% 1.3% 0.2% 2.1% 0.3% 0.1% 0.0% 4.0% 0.2% 25.1% 0.0% 47.6% 10.2% 30.7% 5.5% w/o FGCG w/o Pre-Profile w/o TB (synthetic TB) AutoGate Fig. 5. Ablation study on NVDLA partitions in log scale. Ablation I: FGCG Clustering Algorithm. To isolate the impact of the FGCG clustering algorithm, we compare three clustering strategies while keeping the remainder of the AUTO- GATE flow unchanged. Fig. 6 compares the proposed adaptive stability clustering against K-means and fixed-threshold stabil- ity clustering [12]. Adaptive stability clustering consistently achieves the largest dynamic-power reduction, demonstrating the effectiveness of automatic threshold discovery. counterboothdeframerdividemriscaes 0 20 40 60 80 Dyn. power improv. (%) 43.2% 80.0% 15.0% 0.1% 27.8% 0.1% 55.3% 80.0% 10.2% 55.1% 27.9% -0.8% 55.3% 86.2% 17.6% 58.9% 53.3% 24.5% K-means Fixed Stability Adaptive Stability Fig. 6. Comparison of dynamic power reduction achieved by K-means, fixed- stability, and Adaptive Stability (ours) on small benchmarks. E. Proprietary Production Design Results To evaluate generalization beyond open-source benchmarks, we apply AUTOGATE to two highly optimized proprietary production designs that are several times larger than NVDLA and BlackParrot. Table VII reports dynamic-power and area changes across workloads. “Single” indicates that AUTOGATE uses only Workload 1 for FGCG optimization, while “Com- bined” indicates that the optimization target includes both Workload 1 and Workload 10, representing two distinct activity patterns. For Design A, single-workload optimization improves 9/13 workloads and achieves a 5.92% average dynamic- power reduction, while combined optimization improves 12/13 workloads and achieves a 6.86% reduction. For Design B, the corresponding results improve from 6/13 workloads and 0.29% average reduction to 12/13 workloads and 0.45% average reduction. Area overhead remains below 1% in all cases. These results indicate that optimizing over more diverse workloads can mitigate potential overfitting to a specific workload. A more detailed discussion is provided in Section V. Table VII. Dynamic power and area change on proprietary production designs across all workloads. Design ADesign B WorkloadSingleCombinedWorkloadSingleCombined Workload 1 −3.72% ↓ −2.83% ↓Workload 1 −2.01% ↓ −0.36% ↓ Workload 2 −4.39% ↓ −3.63% ↓Workload 2 −2.85% ↓ −0.97% ↓ Workload 3 −9.29% ↓ −8.67% ↓Workload 3+1.36% ↑ −0.16% ↓ Workload 4 −4.50% ↓ −3.68% ↓Workload 4+1.24% ↑ −0.17% ↓ Workload 5 −9.49% ↓ −8.81% ↓Workload 5 −2.93% ↓ −0.26% ↓ Workload 6 −15.16% ↓ −14.92% ↓Workload 6 −6.50% ↓ −0.47% ↓ Workload 7 −16.49% ↓ −16.23% ↓Workload 7 −1.38% ↓ −1.09% ↓ Workload 8 −17.95% ↓ −17.66% ↓Workload 8+0.10% ↑0.00% Workload 9 −12.43% ↓ −12.92% ↓Workload 9+3.03% ↑ −0.12% ↓ Workload 10+1.24% ↑ −2.35% ↓Workload 10+3.47% ↑ −0.25% ↓ Workload 11+1.78% ↑ −2.04% ↓Workload 11+2.88% ↑ −0.84% ↓ Workload 12+2.66% ↑ −1.60% ↓Workload 12+0.09% ↑ −0.29% ↓ Workload 13+10.73% ↑+6.14% ↑Workload 13 −0.24% ↓ −0.84% ↓ Average −5.92% −6.86%Average −0.29% −0.45% Area ∆ −0.38%+0.42%Area ∆+1.00%+0.02% V. LIMITATIONS AUTOGATE relies on workload-derived switching activity and may therefore overfit to the optimization workload. This workload dependence is especially evident on small designs, where the LLM can analyze the entire RTL design and testbench patterns, enabling workload-specific clock-gating optimizations that achieve up to 86.21% power reduction. On large repository- scale designs, this effect is reduced because the increased design complexity and context size make it more difficult to specialize optimizations to a single workload, although the issue can still exist. As shown in Table VII, optimizing for Workload 1 alone improves dynamic power under that workload, but can degrade results on Workloads 10–13. To mitigate this effect, multiple representative workloads can be incorporated during optimization. Although this may reduce savings on individual workloads, it improves overall power reduction and robustness across diverse workloads. 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