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PCBnet: A Dataset and Automatic Construction of SPICE Netlists from Schematic Images
Zhen Huang, Yuhao Gao, Yuzhi Liu, Daian Cheng, Chengyuan Shao, Yucheng Chen, Yongjian Jia, Futing Zhang, Yichen Shi, Wenhao Wang, Zuyan He, Yangbo Wei, Zhanfei Chen, Jinlong Yan, Yu Zhang, Haoying Wu, Ting-Jung Lin, Lei He
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Status: succeeded | Model: Gemma-4-26B-A4B | Prompt: intel-v1 | Confidence: 92%
Last extracted: 8/31/2026, 3:41:06 AM
Summary
The paper introduces PCBnet, a large-scale dataset for PCB schematic understanding containing over 300 designs with annotated components, pins, wires, texts, and paired SPICE netlists. It also presents an automated schematic-to-netlist pipeline that combines visual recognition (YOLOv11, PaddleOCR, U-Net) with a multi-agent correction framework using LLMs and domain knowledge, achieving high accuracy in component detection (94.54% mAP), text recognition (98.57% accuracy), and connectivity reconstruction (84.47%).
Entities (10)
Relation Signals (8)
PCBnet → contains → SPICE Netlist
confidence 95% · PCBnet... comprising over 300 real-world designs with annotated pins and paired SPICE netlists.
PCBnet → usedfor → PCB schematic understanding
confidence 95% · PCBnet, a large-scale dataset for PCB schematic understanding and netlist construction.
YOLOv11 → usedfor → Component Detection
confidence 95% · YOLOv11 detects the component set
PaddleOCR → usedfor → text recognition
confidence 95% · Text regions are localized by YOLOv11 and recognized by PaddleOCR
U-Net++ → usedfor → Wire Segmentation
confidence 95% · Wire structures are extracted using the original U-Net architecture
LLM → usedfor → Correction
confidence 90% · we employ an LLM-based correction agent augmented with a lightweight domain knowledge base.
PCBnet → outperforms → DeepPCB
confidence 80% · Public PCB datasets are also limited, and most of them, such as DeepPCB... focus on defect detection rather than schematic understanding.
PCBnet → outperforms → HRIPCB
confidence 80% · Public PCB datasets are also limited, and most of them, such as DeepPCB, HRIpcb... focus on defect detection rather than schematic understanding.
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Abstract
Abstract:Printed circuit boards (PCBs) are fundamental to modern electronic systems, yet AI-driven PCB design automation remains constrained by the lack of large-scale paired schematic-netlist datasets. PCB schematics are particularly challenging due to diverse component types, complex wiring topologies, and noisy textual annotations. To address this gap, we present PCBnet, a large-scale PCB schematic dataset comprising over 300 real-world designs with annotated pins and paired SPICE netlists. It contains more than 50,000 component instances, 150,000 wires, 100,000 text regions, and 400,000 characters. We further develop an automated schematic-to-netlist pipeline that combines visual recognition, topology construction, and domain-knowledge-guided multi-agent correction. The proposed method achieves 94.54% component detection mAP, 98.57% text recognition accuracy, and 84.47% end-to-end connectivity accuracy. PCBnet provides a benchmark and data foundation for future AI-driven PCB design automation.
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- Source: https://arxiv.org/abs/2608.27923v1
- Canonical: https://arxiv.org/abs/2608.27923v1
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PCBnet: A Dataset and Automatic Constructing of SPICE Netlists from Schematic ImagesThanks: *Equal contribution.Thanks: † authors: Ting-Jung Lin (tlin@idt.eitech.edu.cn), Lei He (lhe@eitech.edu.cn). Zhen Huang1,3,4,*, Yuhao Gao2,*, Yuzhi Liu2, Daian Cheng2, Chengyuan Shao2, Yucheng Chen2, Yongjian Jia2, Futing Zhang2, Yichen Shi1, Wenhao Wang2, Zuyan He2, Yangbo Wei1, Zhanfei Chen2, Jinlong Yan2, Yu Zhang3, Haoying Wu5, Ting-Jung Lin1,2,4,† , Lei He1,2,4,† Affiliation: Affiliation: 1Eastern Institute of Technology, Ningbo, China 2Ningbo Institute of Digital Twin, Eastern Institute of Technology, Ningbo, China 3University of Science and Technology of China, Hefei, China 4Engineering Research Center of Chiplet Design and Manufacturing of Zhejiang Province 5Wuhan University of Technology, Wuhan, China Affiliation: Abstract PCBs are fundamental to modern electronic systems, yet AI-driven PCB design automation remains constrained by the lack of large-scale paired schematic–netlist datasets. PCB schematics are particularly challenging due to diverse component types, complex wiring topologies, and noisy textual annotations. To address this gap, we present PCBnet, the first large-scale PCB schematic dataset, comprising over 300 real-world designs with annotated pins and SPICE netlists. It contains more than 50,000 component instances, 150,000 wires, 100,000 text regions, and 400,000 characters. We further develop an automated schematic-to-netlist pipeline that combines visual recognition with domain-knowledge-guided multi-agent correction. The proposed method achieves 94.54% component detection mAP, 98.57% text recognition accuracy, and 84.47% end-to-end connectivity accuracy. PCBnet provides a benchmark and data foundation for future AI-driven PCB design automation. Index Terms: PCB dataset, PCB schematic design, netlist generation, electronic design automation I Introduction PCBs are the hardware foundation of modern intelligent systems, including autonomous vehicles, robotics, AI accelerators, and edge devices. However, PCB design remains largely manual due to diverse component types, complex wiring topologies, and heterogeneous design conventions, creating a major bottleneck in electronic product development. AI has shown strong potential in Electronic Design Automation (EDA) [1, 2, 3, 4]. For integrated circuits (ICs), recent works such as ChipNemo [5] demonstrate that foundation models trained on high-quality domain-specific data can capture design knowledge and support automated workflows. In analog and mixed-signal (AMS) design, the AMSnet series [6, 7, 8, 9] further shows the value of multimodal datasets and structured knowledge for circuit understanding and generation. Fig. 1: Overview of PCBnet: the proposed pipeline reconstructs circuit netlists from PCB schematics through visual recognition, topology construction, and multi-agent correction. Despite these advances, AI-driven PCB design still lacks large-scale structured data. Existing PCB data is scattered across datasheets, evaluation-board documents, and open-source repositories, often in heterogeneous and unstructured formats. Public PCB datasets are also limited, and most of them, such as DeepPCB, HRIpcb [10], and related datasets [11, 12], focus on defect detection rather than schematic understanding. As a result, there is still no large-scale schematic–netlist paired dataset for modeling PCB circuit topology. To address this gap, we present PCBnet, a large-scale dataset for PCB schematic understanding and netlist construction. PCBnet contains over 300 real-world PCB designs with multi-level annotations, including components, pins, wires, texts, and SPICE netlists. It covers more than 50,000 component instances, 150,000 wire annotations, 100,000 text regions, and 400,000 labeled characters. As shown in Fig. 1, we further develop a schematic-to-netlist pipeline that integrates visual element recognition, topology construction, and multi-agent correction with domain knowledge. On PCBnet, our method achieves 94.54% component detection mAP, 98.57% text recognition accuracy, and 84.47% connectivity accuracy, demonstrating the effectiveness of PCBnet as both a dataset and benchmark for AI-driven PCB design automation. The main contributions of this work are summarized as follows. • PCBnet Dataset. We introduce the first large-scale PCB schematic dataset with detailed annotations of components, pins, wires, texts, and paired SPICE netlists. • Schematic-to-Netlist Framework. We propose a pipeline that combines visual recognition, structure construction, and multi-agent correction to recover circuit connectivity from schematic images. • PCB Schematic Benchmark. We establish a benchmark for component detection, text recognition, and netlist construction, providing a data foundation for future AI-driven PCB design research. Fig. 2: Overview of the schematic-to-netlist pipeline. Stage 1 extracts visual elements, including components, wires, and texts, from input PCB schematics. Stage 2 performs structure construction and element matching. Stage 3 applies a multi-agent correction framework, supported by a knowledge base via RAG, to correct and complete the final structured SPICE netlist. I Dataset Construction I-A Dataset Collection and Annotation PCBnet is constructed from over 300 real-world PCB schematic files collected from open-source hardware projects and EDA tools, including KiCad and EasyEDA. The designs cover diverse circuit types, component categories, wiring structures, and schematic styles. For each design, we render the schematic image and extract the corresponding SPICE netlist from the original engineering file, ensuring one-to-one image–netlist correspondence. Each schematic is annotated with component bounding boxes, pin locations, text regions, and wire masks. Component and text annotations are initialized using pretrained models and manually corrected for accuracy. I-B Connectivity Representation and Statistics Each schematic is represented as a circuit graph G=(V,E),G=(V,E), (1) where V denotes component pins and E denotes electrical connections. Let pi,kp_i,k be the k-th pin of component i and wmw_m a wire segment. A pin–wire connection is established if d(pi,k,wm)<ϵ,d(p_i,k,w_m)<ε, (2) where ϵε is a distance threshold. The resulting pin–wire associations are used to construct the circuit graph and generate the SPICE netlist. I Image-to-Netlist Pipeline Given a PCB schematic image I, the framework reconstructs its circuit topology and generates a structured SPICE netlist. As shown in Fig. 2, it consists of three stages: Visual Element Extraction, Circuit Structure Construction, and Multi-agent Correction. I-A Stage 1: Visual Element Extraction Component Detection. YOLOv11 detects the component set C=ciC=c_i, where each component is represented by a bounding box bib_i and category label lil_i. Text Recognition. Text regions are localized by YOLOv11 and recognized by PaddleOCR [13]. For vertically oriented labels, OCR is applied to both the original crop and its 90∘90 -rotated version, and the higher-confidence result is selected. The recognized text set is denoted as T=(ti,bi,ci),T=\(t_i,b_i,c_i)\, where tit_i is the recognized token, bib_i is the text bounding box, and cic_i is the OCR confidence score. I-A1 Wire Segmentation Wire structures are extracted using the original U-Net architecture with default settings. Given the input image I, the network predicts a binary wire mask M=Seg(I)M=Seg(I), where M(x,y)=1M(x,y)=1 indicates a wire pixel. We further apply skeletonization to obtain a one-pixel-wide representation of the wiring topology, denoted as W=wkW=\w_k\. I-B Stage 2: Structure Construction After obtaining components C, texts T, and wires W, Stage 2 constructs the circuit topology through two steps: geometric construction and text-component matching. I-B1 Construction We first construct the geometric structure of the circuit by estimating pin locations and inferring electrical connectivity. Pin Estimation. Pin locations are estimated based on component categories and geometric layouts. Common component types, such as resistors, capacitors, and integrated circuits, typically exhibit consistent pin configurations, allowing candidate pin locations to be derived in a geometry-guided manner. Connectivity Inference. We infer electrical connections by analyzing the spatial relationships between estimated component pins and wire segments. Each pin is treated as a node, and a connection is established when a pin is spatially adjacent to a wire segment. The resulting circuit topology is represented as a graph G=(V,E)G=(V,E), where V denotes component pins and E denotes the inferred electrical connections. I-B2 Text-Component Matching After constructing the geometric topology, we associate textual labels with their corresponding components. The matching process combines spatial proximity with schematic-specific naming conventions and layout characteristics. For each text instance tit_i, we first identify candidate components in its local neighborhood and obtain an initial association using nearest-neighbor matching based on Euclidean distance. This approach is effective for regular schematic layouts, where component identifiers are generally placed close to their corresponding components. However, dense layouts, wire occlusions, and flexible text placement can make nearest-neighbor matching ambiguous. We therefore refine the initial associations using three lightweight constraints: • Category Consistency Constraint: Text prefixes such as ‘R”, ‘C”, and “U” are required to agree with the corresponding component categories, reducing cross-type mismatches. • Geometric Alignment Constraint: Text-component pairs with horizontal or vertical alignment are prioritized according to common schematic layout conventions. • Local Uniqueness Constraint: Conflicting assignments are reduced by preventing multiple text instances within a local region from being matched to the same component. By combining distance-based matching with these structured constraints, the proposed method improves the robustness of text-component association. The matched components, pins, wires, and textual labels are then organized into a structured circuit topology and converted into a SPICE netlist. I-C Stage 3: Multi-agent Correction Stage 2 produces an initial circuit topology, but recognition errors, particularly in text, may propagate into structural inaccuracies such as misidentified components or incorrect net labels. OCR errors often follow common patterns, including missing underscores and confusion between visually similar characters (e.g., 1/l/I and O/0). Since these errors are difficult to resolve through visual processing alone, Stage 3 introduces a multi-agent correction framework that integrates recognition results with domain-specific knowledge. I-C1 Confidence-Guided Gatekeeper A gatekeeper module first filters OCR outputs based on confidence. Predictions with ci≥τc_i≥τ are accepted directly, while low-confidence tokens are routed to the correction module. This design focuses computation on uncertain cases and avoids unnecessary overhead. I-C2 LLM-based Correction with Domain Knowledge For low-confidence tokens, we employ an LLM-based correction agent augmented with a lightweight domain knowledge base. The knowledge base encodes naming conventions, common character confusion patterns, and representative correction examples observed in PCB schematics. Given an OCR token tit_i, the system retrieves relevant rules ℛiR_i and performs constrained generation: t^i(L)=argmaxtP(t∣ti,ℛi), t_i^(L)= _t\;P(t t_i,R_i), where t^i(L) t_i^(L) denotes the corrected token. This design improves correction accuracy while restricting outputs to valid naming patterns. I-C3 Multi-modal Image correction When rule-based correction is insufficient, we introduce a multimodal correction step that directly leverages visual information. The cropped text image IiI_i is fed into a vision-language model (e.g., GPT-4.1 / GPT-5.4) to produce a candidate: t^i(V)=fvlm(Ii). t_i^(V)=f_vlm(I_i). The final prediction is selected based on confidence: t^i=t^i(V),if c(t^i(V))>c(ti)ti,otherwise. t_i= cases t_i^(V),&if c( t_i^(V))>c(t_i)\\ t_i,&otherwise. cases This module is particularly effective for short text tokens, where visual models tend to be more reliable. Moreover, since most tokens are already correctly recognized in earlier stages, this correction is only applied to a small subset of cases and thus introduces limited additional overhead. I-C4 Component-Aware Pairing To further reduce ambiguity, each low-confidence token is paired with its associated component obtained from the text-component matching in stage I-B. Specifically, we use the category of the matched component as a semantic constraint: t^i(C)=argmaxtP(t∣ti,lj), t_i^(C)= _t\;P(t t_i,l_j), where ljl_j denotes the category of the corresponding component. This constraint (e.g., R for resistors, C for capacitors) improves correction accuracy in ambiguous cases. Finally, by integrating visual element extraction, Structure construction, and multi-agent correction, the proposed framework enables reliable and consistent schematic-to-netlist construction. IV Experiments IV-A Experimental Setup and Evaluation We split PCBnet into training, validation, and test sets at the design level with a ratio of 8:1:1. All experiments are implemented in PyTorch and conducted on a workstation with an NVIDIA RTX 3090 GPU and an Intel Core i9 processor. We evaluate the full pipeline on three tasks: • Component Detection, evaluated by mean Average Precision (mAP); • Text Recognition, evaluated by Character Error Rate (CER), Word Error Rate (WER), and accuracy (ACC); • Netlist Construction, evaluated by connectivity accuracy, i.e., the proportion of correctly recovered pin-to-pin connections. IV-B Component Detection Results We first evaluate component detection performance on PCBnet using mAP. Our method achieves 94.54% mAP, demonstrating strong detection performance across diverse PCB schematic layouts. PCB schematics contain substantial variation in component types, symbol styles, scales, and orientations. In addition, real-world layouts are often dense and contain overlapping visual elements, making accurate localization nontrivial. The high mAP shows that the proposed detection module can reliably localize and classify components under these challenging conditions. In contrast, even when provided with cropped component regions, general-purpose multimodal models (e.g., GPT-5.4, Claude Opus 4.6, and Gemini 3 Pro) achieve substantially lower accuracy (around 30%). When applied directly to full schematic images, these models often fail to reliably localize individual components due to the dense and fine-grained layout, highlighting their limitations in precise localization and structured visual parsing required for schematic understanding. TABLE I: Comparison of component detection, wire extraction, and netlist construction accuracy. Method Comp. mAP Wire. IoU Conn. Acc. Ours (PCBnet) 94.54 93.70 84.47 GPT-5.4 34.28 – 8.74 Claude Opus 4.6 29.63 – 7.91 Gemini 3 Pro 33.05 – 9.26 DeepSeek-V3.2 27.17 – 7.02 Qwen3.5-Plus 29.44 – 8.01 IV-C Text Recognition Results Table I compares different OCR engines on the PCB schematic dataset, including Tesseract [14], EasyOCR [15], MMOCR [16], and DocTR [17]. We consider two settings: Full Image Mode, where OCR is applied directly to the entire schematic, and YOLO+ Mode, where text regions are first localized before recognition. TABLE I: Comparison of OCR engines under full-image and detection-assisted settings. Mode Method CER (%) WER (%) ACC (%) Full Image PaddleOCR 21.35 37.40 78.65 EasyOCR 60.34 94.68 39.66 Tesseract 22.34 42.16 77.66 DocTR 22.99 50.00 77.01 MMOCR 39.02 50.77 60.98 YOLO+ PaddleOCR 6.33 19.04 93.67 EasyOCR 49.90 85.83 50.10 Tesseract 50.84 70.80 49.16 DocTR 13.86 32.40 86.14 MMOCR 16.61 33.10 83.39 TrOCR 13.26 35.95 86.74 TABLE I: Ablation study of the multi-agent correction modules. Method CER (%) WER (%) ACC (%) YOLO+PaddleOCR 6.33 19.04 93.67 + Knowledge-guided LLM 4.07 8.45 95.93 + Multimodal Image Agent 2.52 4.67 97.48 + Component Pairing 1.43 3.59 98.57 All methods perform poorly in the Full Image setting, with CER typically above 20% and WER above 40%. This indicates that directly applying OCR to full schematic images is highly susceptible to background noise, dense layouts, and non-text elements. By contrast, the YOLO+ setting significantly improves performance across all methods, showing that accurate text localization is important for robust schematic OCR. Among them, YOLO+PaddleOCR achieves the best performance, with 6.33% CER, 19.04% WER, and 93.67% ACC. This result confirms the effectiveness of decoupling text detection and recognition in complex schematic images. To further improve recognition performance, we incrementally add each module of the proposed multi-agent correction mechanism to the YOLO+PaddleOCR baseline. The results are shown in Table I. Each module consistently improves recognition performance. The knowledge-guided LLM reduces CER from 6.33% to 4.07%, showing that domain-specific rules can effectively resolve common OCR ambiguities. The multimodal image agent further lowers CER to 2.52%, indicating that visual information is beneficial for handling ambiguous or degraded text regions. Finally, component-aware pairing reduces CER to 1.43% and WER to 3.59%, achieving an overall accuracy of 98.57%. IV-D Netlist Construction Results Table I compares the end-to-end schematic-to-netlist construction results. Our method achieves 93.70% wire extraction accuracy and 84.47% connectivity accuracy, where connectivity accuracy measures the proportion of correctly recovered pin-to-pin connections. In comparison, general-purpose multimodal models achieve approximately 30% component accuracy and below 10% connectivity accuracy. These results highlight their difficulty in capturing the fine-grained geometric and topological structures of PCB schematics. By explicitly constructing circuit topology from recognized components, wires, and their structural relationships, our framework provides substantially more reliable netlist reconstruction. V Conclusion In this work, we present PCBnet, a large-scale dataset for PCB schematic understanding and schematic-to-netlist construction. PCBnet provides multi-level annotations for components, pins, wires, texts, and paired SPICE netlists, covering over 50k component instances, 150k wires, 100k text regions, and 400k labeled characters. We further develop a topology-oriented image-to-netlist framework that integrates visual recognition, structure construction, and multi-agent correction to recover circuit connectivity. Experiments show that our method achieves 94.54% component detection mAP, 98.57% text recognition accuracy, and 84.47% connectivity accuracy. PCBnet establishes a benchmark and data foundation for future AI-driven PCB design automation. References [1] J. Chaudhuri, A. Chaudhuri, and K. Chakrabarty (2025) LATENT: llm-augmented trojan insertion and evaluation framework for analog netlist topologies. In 2025 IEEE International Conference on LLM-Aided Design (ICLAD), p. 133–140. Cited by: §I. [2] Y. Wei, Z. Huang, L. He, L. Huang, T. Lin, and W. W. Xing (2026) VFlow: discovering optimal agentic workflows for Verilog generation. In 2026 31st Asia and South Pacific Design Automation Conference (ASP-DAC), p. 355–361. External Links: Document, Link Cited by: §I. [3] Z. Huang, H. Wang, W. Yang, M. Tang, D. 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