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ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation
Zhongkai Yu, Yichen Lin, Chenyang Zhou, Yuwei Zhang, Kun Zhou, Junxia Cui, Haotian Ye, Zhengding Hu, Zaifeng Pan, Ruiyi Wang, Yujie Zhao, Hejia Zhang, Jingbo Shang, Jishen Zhao, Yufei Ding
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Status: succeeded | Model: Gemma-4-26B-A4B | Prompt: intel-v1 | Confidence: 93%
Last extracted: 7/8/2026, 2:40:04 PM
Summary
ChipMATE is a self-trained multi-agent framework for RTL code generation that pairs a Verilog agent with a Python reference-model agent to mutually verify outputs without a golden oracle. It introduces a backtrack mechanism to prevent error propagation, a two-stage training pipeline (single-agent SFT/RL followed by joint multi-agent RL), and a hybrid data-generation framework to produce 64.4K training samples. ChipMATE achieves 75.0% and 80.1% pass@1 on VerilogEval V2 using 4B and 9B base models, outperforming existing self-trained models and large proprietary models like DeepSeek V4.
Entities (13)
Relation Signals (12)
ChipMATE → achieves → 75.0% pass@1 on VerilogEval V2
confidence 96% · ChipMATE achieves 75.0% and 80.1% pass@1 on VerilogEval V2 with 4B and 9B base models
ChipMATE → achieves → 80.1% pass@1 on VerilogEval V2
confidence 96% · ChipMATE achieves 75.0% and 80.1% pass@1 on VerilogEval V2 with 4B and 9B base models
UCSD → published → ChipMATE
confidence 96% · Zhongkai Yu ∗ UCSD La Jolla, USA ... Yufei Ding UCSD La Jolla, USA
ChipMATE → uses → Verilog Agent
confidence 95% · ChipMATE pairs a Verilog agent with a Python reference-model agent that mutually verify each other's outputs without any golden oracle.
ChipMATE → uses → Python Reference-Model Agent
confidence 95% · ChipMATE pairs a Verilog agent with a Python reference-model agent that mutually verify each other's outputs without any golden oracle.
ChipMATE → implement → Two-Stage Training Pipeline
confidence 94% · a two-stage training pipeline that first trains each agent individually to saturate its code-generation capability, then trains the team jointly to collaborate effectively.
Two-Stage Training Pipeline → consistsof → Single-Agent Training
confidence 93% · In Stage 1, we train each agent separately with SFT followed by RL to strengthen its individual capability
→ →
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Abstract
Abstract:Existing API-based agentic systems for RTL code generation are fundamentally misaligned with industrial practice: they assume a golden testbench is available at generation time, rely on closed-source APIs incompatible with chip vendors' air-gapped security requirements, and cannot be trained on vendors' proprietary RTL codebases, leaving valuable internal data unused. Recent self-trained models address the deployment constraint but remain single-turn generators that overlook the critical role of verification in real industrial flows. To bridge these gaps, we present ChipMATE, the first self-trained multi-agent framework for RTL generation. Inspired by industrial practice where correctness emerges from cross-comparison between independently written RTL modules and reference models, ChipMATE pairs a Verilog agent with a Python reference-model agent that mutually verify each other's outputs without any golden oracle. We design a backtrack-based inference workflow to prevent error propagation across turns, and a two-stage training pipeline that first trains each agent individually to saturate its code-generation capability, then trains the team jointly to collaborate effectively. To support the training, we further build a hybrid data-generation framework that produces 64.4K high-quality reference model training samples. ChipMATE achieves 75.0\% and 80.1\% pass@1 on VerilogEval V2 with 4B and 9B base models, outperforming all existing self-trained models and even DeepSeek V4 with 1600B parameters. Our code and model weights are publicly available in this https URL.
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- Source: https://arxiv.org/abs/2605.12857v1
- Canonical: https://arxiv.org/abs/2605.12857v1
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ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation Zhongkai Yu ∗ UCSD La Jolla, USA zhy055@ucsd.edu Yichen Lin ∗ UCSD La Jolla, USA yil384@ucsd.edu Chenyang Zhou Columbia University New York, USA cz2791@columbia.edu Yuwei Zhang UCSD La Jolla, USA yuz163@ucsd.edu Kun Zhou UCSD La Jolla, USA kuzhou@ucsd.edu Junxia Cui UCSD La Jolla, USA jucui@ucsd.edu Haotian Ye UCSD La Jolla, USA h5ye@ucsd.edu Zhengding Hu UCSD La Jolla, USA zhh068@ucsd.edu Zaifeng Pan UCSD La Jolla, USA zapan@ucsd.edu Ruiyi Wang UCSD La Jolla, USA ruw079@ucsd.edu Yujie Zhao UCSD La Jolla, USA yuz285@ucsd.edu Hejia Zhang UCSD La Jolla, USA hez024@ucsd.edu Jingbo Shang UCSD La Jolla, USA jshang@ucsd.edu Jishen Zhao UCSD La Jolla, USA jzhao@ucsd.edu Yufei Ding UCSD La Jolla, USA yufeiding@ucsd.edu Abstract Existing API-based agentic systems for RTL code generation are fundamentally misaligned with industrial practice: they assume a golden testbench is available at generation time, rely on closed-source APIs incompatible with chip vendors’ air-gapped security requirements, and cannot be trained on vendors’ proprietary RTL codebases, leaving valuable internal data unused. Recent self-trained models address the deployment constraint but remain single-turn generators that overlook the critical role of verification in real industrial flows. To bridge these gaps, we present ChipMATE, the first self-trained multi-agent framework for RTL generation. Inspired by industrial practice where correctness emerges from cross-comparison between independently written RTL modules and reference models, ChipMATE pairs a Verilog agent with a Python reference-model agent that mutually verify each other’s outputs without any golden oracle. We design a backtrack-based inference workflow to prevent error propagation across turns, and a two-stage training pipeline that first trains each agent individually to saturate its code-generation capability, then trains the team jointly to collaborate effectively. To support the training, we further build a hybrid data-generation framework that produces 64.4K high-quality reference model training samples. ChipMATE achieves 75.0% and 80.1% pass@1 on VerilogEval V2 with 4B and 9B base models, outperforming all existing self-trained models and even DeepSeek V4 with 1600B parameters. Our code and model weights are publicly available in https://github.com/zhongkaiyu/ChipMATE. ∗ Equal contribution. arXiv:2605.12857v1 [cs.MA] 13 May 2026 1 Introduction Large Language Models (LLMs) excel at general-purpose programming but struggle with Register- Transfer Level (RTL) code generation, a cornerstone of modern chip design, largely due to the scarcity of high-quality RTL data in public corpora. To improve RTL generation quality, recent agentic workflows like MAGE [35] and VerilogCoder [8] orchestrate LLMs through task decomposition and iterative self-correction, achieving promising results on academic benchmarks. Despite these advances, current agentic RTL pipelines are fundamentally misaligned with industrial chip-design practice in three coupled ways, preventing their adoption by chip vendors. First, existing workflows require a golden testbench to drive self-correction, which does not hold for industrial settings. In real production, testbenches are written by dedicated verification engineers and do not exist before the RTL is written. Moreover, even when a testbench exists, it is often imperfect and may itself contain bugs, making it unsuitable to serve as a golden oracle. Second, these workflows depend on LLM APIs, which conflict with the security posture of chip vendors. RTL code is treated as first-class intellectual property, and core development servers are routinely air-gapped to prevent any data leakage to third-party endpoints. Third, the API-centric design wastes chip companies’ most valuable asset for LLM improvement: their internal RTL codebases. Years of production-grade RTL, far superior to any publicly available training data, remain entirely unused because API-based LLMs cannot be fine-tuned on proprietary code. To address these constraints, recent efforts such as QiMeng-CodeV-R1 [37] and RTLSeek [33] train open-source LLMs that run on chip vendors’ local servers, removing the dependency on external APIs and enabling training with in-house codebases. Moreover, these models generate code in a single turn, eliminating the need for golden testbenches. While this avoids the above issues, single-turn generation offers no mechanism for the model to check or correct its own output, resulting in low code accuracy. This is unsurprising, as even a senior design engineer rarely writes correct RTL in one attempt. Indeed, chip design industry has realized this problem and does not ensure code correctness by demanding perfection from any single engineer, but through a cross-verification workflow between design engineers and verification engineers. Specifically, design engineers implement a module in RTL while verification engineers independently write a reference model in a high-level language (e.g., Python, SystemC, or C++) that predicts the RTL module’s cycle-accurate behavior. Since neither side is assumed correct, the two parties iteratively compare outputs, locate bugs, and apply fixes until the design is verified. This industrial workflow directly inspires our work ChipMATE, a multi-agent system in which one agent generates Verilog in the role of a design engineer and another generates a Python reference model in the role of a verification engineer. The two agents work as a team, iteratively cross-verifying each other to produce high-quality RTL code. However, building such a self-trained multi-agent workflow introduces three key challenges. (C1) Error propagation without a golden oracle. Since neither agent generates perfect code, a mismatch between the design agent and the verification agent does not reveal which side is wrong. Naively asking one agent to “correct” the other can compound errors turn by turn, producing worse results than a single-model baseline. (C2) Weak individual capability and lack of collaboration. Off- the-shelf open-source models such as Qwen3.5-4B/9B achieve below 45% accuracy on both Verilog generation and reference-model generation, even on simple benchmarks like VerilogEval V2 [19]. Each agent’s individual capability must therefore be strengthened through dedicated training before any meaningful collaboration can occur. Beyond individual competence, the two agents must also learn to work as a team, a skill that standard single-model training does not provide. (C3) No training data for reference-model generation. Reference-model generation is a largely unexplored task with no publicly available training data. One might hope to bootstrap a dataset by distilling from strong API-based LLMs, but even DeepSeek-R1 achieves below 20% pass@1 when converting the Verilog- based QiMeng training set into Python reference models, making direct distillation impractical. The poor performance stems from the unique demands of reference-model generation, which requires predicting cycle-accurate hardware behavior and adhering to two’s-complement arithmetic patterns, tasks that LLMs are never exposed to during pretraining. We present ChipMATE, the first self-trained multi-agent framework for RTL generation that supports fully offline deployment. 1. Cross-verification multi-agent workflow (C1). We propose an agentic workflow in which a Verilog agent and a Python reference-model agent mutually verify each other’s outputs. 2 Step1: RTL and Ref Model Gen x N ... x N ... (a) Cross-verification multi-agent workflow Each agent samples N candidates from its system prompt independently. Compare Verilog code with Python code and generate mismatch info. Waveform Mismatch Info Verilog Agent Sys Prompt Python Agent Sys Prompt Prompt with mismatch info Prompt with mismatch info Agents self-correct using mismatch info. A correction is accepted only if it strictly improves the match rate (backtrack mechanism). 12 Turn1 60% Match Turn2 70% Match 3 Turn3 65% Match 4 Backtrack Mechanism Cross-Verify Tool Step2: Cross VerificationStep3: Multi-Turn Self-Correction Verilog Agent Python Agent Stage1: Single-Agent Training SFTRL Data FilteringSingle-Agent RL pass@10∈ [0.1, 0.9] SFT imparts basic domain knowledge to each agent. Data filtering ensures productive RL signal. Single-agent RL refines generation quality through reward-driven exploration. Stage2: Multi-Agent Training MA-RL Data FilteringMulti-Agent RL Filtering The two agents are trained jointly so they learn how to collaborate. Python Agent Training Data Gen LLM API Distillation IR-Based Conversion Category Specific Augmentation Open-source Verilog Data Python Ref Model Data Verilog Python SFT Data RL Data (b) Two-stage training pipeline(c) Python ref model train data generation pass@10∈ [0.1, 0.9] Figure 1: Overview of ChipMATE. (a) ChipMATE introduces multi-agent cross-verification with a backtrack mechanism. (b) The training pipeline of ChipMATE has two stages, and we build a hybrid reference-model data generation framework. To prevent error propagation across turns, we introduce a backtrack mechanism that auto- matically reverts to a previous turn whenever the current turn produces worse results. To support this workflow, we build cross-language comparison tools that align Verilog and Python outputs, along with error-explanation tools that translate raw waveform mismatches into natural-language diagnostics the agents can act on. We also design structured sys- tem prompts with code skeletons and detailed implementation guidance to deliver clear instructions and enhance model performance. 2.Two-stage training pipeline (C2). We design a two-stage training pipeline with dedicated dataset curation and reward functions. In Stage 1, we train each agent separately with SFT followed by RL to strengthen its individual capability on Verilog module and Python reference-model generation, since multi-agent collaboration requires each constituent agent to be sufficiently competent. In Stage 2, we introduce a multi-agent RL algorithm paired with a multi-level reward function that trains the two agents jointly, teaching them to collaborate effectively and further boosting end-to-end generation quality. 3. Hybrid data-generation framework for reference models (C3). To address the complete absence of reference-model training data, we develop a hybrid data-generation framework that combines agentic API-based synthesis with IR-level code conversion, transforming existing Verilog datasets into high-quality, chain-of-thought-augmented Python reference- model samples. We further apply targeted augmentation on task categories where LLM performance is weakest, ensuring balanced and comprehensive training coverage. 4. Open-source release. We have released all model weights for the ChipMATE series (4B and 9B) and the complete multi-agent workflow implementation to facilitate future research. 2 Methods 2.1 Overview As shown in Figure 1, ChipMATE consists of three components: a cross-verification multi-agent workflow (subsection 2.2) in which a Verilog agent and a Python reference-model agent iteratively refine their outputs through cross-verification, a two-stage training pipeline (subsection 2.3) that first trains each agent individually and then jointly via multi-agent RL, and a hybrid data generation framework (subsection 2.4) that creates reference-model training data from scratch. 3 S0 a 0 0 S 1 0 a 0 1 a 0 2 (a) Normal GRPO only works for sparse reward S 1 1 S 1 2 a 1 0 a 1 1 a 1 2 S 2 0 S 2 1 S 2 2 Reward S0 a 0 0 S 1 00 a 0 1 a 0 2 S 1 10 S 1 20 Reward V 0 V 1 V2 P 0 P 1 P 2 (b) X-GRPO to support the multi-agent RL in ChipMATE and our KxK sampling S 1 01 S 1 11 S 1 21 S 1 02 S 1 12 S 1 22 a 2 0 a 2 1 a 2 2 S 3 0 S 3 1 S 3 2 S i 00 S i 01 S i 02 S i 10 S i 11 S i 12 S i 20 S i 21 S i 22 a 1 0 a 1 1 a 1 2 S 2 00 S 2 10 S 2 20 Highest Reward S 2 01 S 2 11 S 2 21 S 2 02 S 2 12 S 2 22 Reward a 2 0 a 2 1 a 2 2 S 3 0 S 3 1 S 3 2 Reward Verilog Agent Python Agent Group Num (K) = 3 Figure 2: (a) Standard GRPO collapses to group size 1 across multi-turn rollouts when dense per-turn rewards are used. (b) X-GRPO, extending AT-GRPO [34], restores meaningful group variance: both agents independently sampleKcandidates per turn, paired index-wise intoK× Kcandidate pairs, of which the best-scoring pair is selected as the shared prefix for the next turn. 2.2 Cross-Verification Multi-Agent Workflow Multi-turn cross-verification workflow.As shown in Figure 1(a), our workflow proceeds in three steps. In the first step, a Verilog agent and a Python reference-model agent each sampleNcandidate implementations from the same natural-language specification, working independently without access to each other’s output. We use Python rather than SystemC as the reference-model language because open-source LLMs are substantially more proficient in it. In the second step, a cross-language comparison tool simulates both outputs on 1000 randomly generated stimuli, records waveforms, and produces structured mismatch diagnostics. In the third step, if outputs disagree, each agent receives the mismatch information and self-corrects over multiple turns. Crucially, agents never see each other’s code and must independently judge whether their own implementation is at fault. To prevent error compounding across turns, we enforce a backtrack mechanism [16,24,3]: a correction is accepted only if it strictly improves the match rate; otherwise the agent reverts to its last accepted version. The loop terminates when outputs agree or the turn limit is reached. Comparison and feedback infrastructure.The cross-verification tool compiles the Verilog mod- ule via Icarus Verilog and executes the Python reference model, then compares their cycle-by-cycle outputs. Since raw waveform files are difficult for LLMs to parse, we additionally build a waveform- to-natural-language converter that locates the first divergent cycle and packages the surrounding input/output context into a structured description that agents can directly understand and act upon. Prompt design.We structure the system prompt to mirror the combinational/sequential separation found in standard RTL textbooks, since LLMs already partially internalize this decomposition from pretraining. Each prompt contains four sections: (1) a code skeleton with the exact module name and parameterized port list, fixing the interface and preventing naming drift across rollouts. This does not constitute an unrealistic advantage, as in industrial practice the input and output signals of every module are strictly defined in specification documents and can be directly converted into a code skeleton. (2) Combinational-logic guidelines covering latch avoidance and full case coverage; (3) sequential-logic guidelines covering reset handling and non-blocking assignment conventions; and (4)a few-shot example demonstrating the desired reasoning-then-code format. This structured prompt alone improves first-attempt pass rate by approximately 1-5% when applied to frontier LLMs via API, confirming it as a model-agnostic source of gain. Full prompt text is provided in Appendix A. 2.3 Two-Stage Training Pipeline As shown in Figure 1, we propose a two-stage pipeline: the first stage trains each agent indepen- dently to maximize individual competence, and the second stage trains both agents jointly to learn collaborative behavior within the cross-verification workflow. Stage 1: Single-agent training.We train the Verilog agent and the Python agent separately on their respective datasets using SFT followed by RL. SFT teaches each agent general knowledge about its target task and enables correct code generation, but with high variance, as evidenced by a large gap between pass@1 and pass@10. To close this gap, we apply GRPO [22], which samples a group ofK candidate outputs for each query and derives group-relative advantages to guide policy optimization. We carefully curate the RL training set by retaining only problems whose post-SFT pass@10 lies in 4 [0.1, 0.9], ensuring that each group produces a productive mix of successes and failures. Problems that are always solved or never solved yield zero-variance advantages and provide no learning signal. We adopt full-parameter fine-tuning rather than LoRA [10] for both SFT and RL. This choice is critical because multi-agent RL in the second stage can only succeed if both participating agents are already strong. If either agent generates consistently poor code, the cross-verification loop produces noisy rewards that prevent meaningful collaboration learning. Stage 2: Multi-agent RL. After Stage 1, both agents already excel at their respective code- generation tasks. Stage 2 teaches them to collaborate within the cross-verification workflow. Specifi- cally, when a mismatch arises, each agent must analyze the diagnostic information, determine whether the fault lies in its own code or the other agent’s, and apply self-correction only when it identifies a genuine error in its own implementation. We introduce two techniques for this stage. X-GRPO trajectory sampling. Standard GRPO is ill-suited to a multi-turn, multi-agent setting [15]. As illustrated in Figure 2(a), assigning a dense reward at the end of each turn causes the effective group size for every turn beyond the first to collapse to one, making group-relative advantage estimation degenerate. To address this, we draw inspiration from Tree-of-Thought [31] and AT-GRPO [34] and propose X-GRPO, a variant of GRPO that restores meaningful within-group variance across turns. Concretely, at each turn, both agents independently generateKcandidates outputs, formingK× K candidate pairs as the evaluation group. After evaluating all pairs, we select the best-performing one as the shared prefix for the next turn and repeat the process. Because all candidates at a given turn share the same prefix, each agent’sKoutputs constitute a proper GRPO group that exhibits sufficient reward variance, keeping the advantage estimation informative throughout the entire trajectory. Formally, for a groupgat turnt, we sampleKcandidate actionsa (c) t K c=1 , evaluate each with a rule-based reward R(·), and compute a mean-centered, normalized advantage A g (a (c) t ). Each agent has its own policyθ (i) , trained on a minibatchB i that pools only that agent’s groups. The clipped surrogate loss is L(θ (i) ) =−E g∈B i " 1 K K X c=1 min r (c,i) g A (c) g , clip r (c,i) g , 1−ε, 1+ε A (c) g # ,(1) wherer (c,i) g = π θ (i) (a (c) g |o g )/π θ (i) old (a (c) g |o g ) is the importance ratio. This formulation separates the two policies’ gradients while still letting them collaborate at rollout time. Hierarchical reward design. Our reward design directly serves the ultimate training goal: teaching both agents to learn from mismatch information and generate better code through multi-turn iteration. The per-agent rewardR (t) a is composed of three components. (1) Local reward (R local ), which independently evaluates each agent’s code correctness through turn-over-turn improvement. It follows a multi-tiered design where the scores∈0, 0.1, 0.2, 0.2 + 0.8ccorresponds to compile failure, runtime error, I/O port mismatch, and partial pass ratec, respectively. An agent receives the next tier of reward only after clearing all previous tiers, encouraging syntactically correct, high- pass-rate code. (2) Correct-fix bonus (R fix ), a sparse binary reward for successfully resolving a previously mismatched stimulus. It is awarded only when a mismatch from the previous turn is fixed, and both agents produce the correct output at that stimulus cycle. If the two agents agree but their shared output is wrong, this reward is withheld. This teaches agents to fix mismatches correctly rather than to merely converge on an arbitrary answer. (3) Team-match reward (R match ), a dense reward proportional to the overall match ratio between the two agents’ outputs, providing a smooth gradient toward mutual agreement. The aggregate reward is R (t) a = δ local · R (t) local,a + δ fix · R (t) fix + δ match · R (t) match ,(2) where we setδ local = 10,δ fix = 0.2, andδ match = 0.5. The largeδ local makes individual code improvement the dominant training signal, the binaryδ fix provides rare but high-quality debugging reward, and the moderateδ match acts as a dense regularizer that steers both agents toward agreement without dominating the optimization. 2.4 Hybrid Reference-Model Data Generation The two-stage training pipeline requires substantial data for both agents. Existing public datasets with chain-of-thought annotations already meet the need for Verilog agent training, but no comparable 5 resource exists for the Python reference-model agent. To bridge this gap, we build a hybrid generation framework combining three complementary pipelines, as illustrated in Figure 3. LLM-API agentic distillation. We call a frontier LLM to generate a Python reference model for each Verilog module, then verify it against the golden Verilog with our cross-language comparator. When mismatches are detected, diagnostic information is fed back for iterative self-correction. This pipeline produces samples with CoT reasoning, but suffers from high cost and low yield: on the 87K-sample QiMeng-CodeV [37] dataset, DeepSeek-R1 [6] achieves only 17% single-turn and 35% two-turn success rates. Processing the full dataset with four API keys in parallel costs over $2,000 and more than 200 hours, ultimately producing only about 25K verified samples. IR-based conversion.Since 25K samples alone are insufficient to train a strong model, we introduce a deterministic conversion pipeline for the remaining 62K samples. The low LLM success rate likely arises because LLMs are never explicitly trained to replicate Verilog semantics in Python. Our pipeline sidesteps this difficulty by operating at the abstract syntax tree (AST) level, reserving LLM calls solely for appending chain-of-thought [29] annotations to already-correct code. The pipeline proceeds in three stages. (1) Parsing. We parse the reference Verilog with PYVERILOG [25] and normalize its structures, including ports, signals, continuous assignments, combinational and sequential blocks into a uniform intermediate representation (IR). (2) Behavioral lowering. Each combinational block is converted into a pure Python function whose output depends solely on its current inputs. Each sequential block, triggered onposedge clk, becomes a per-cycle update function that applies explicit bit-width masks to preserve two’s-complement semantics. (3) Top-module wrapping. The translated functions are assembled into aTopModuleclass whose port interface mirrors the original Verilog module, enabling it to be directly tested with our cross-verification tool. This pipeline is cost-free, completes in under two hours, and yields 36K additional verified samples. Its principal limitation is the unreal CoT appended by LLM after the Python module is generated and verified. LLM-API Pass? Verify ≈ 25K LLM-API Agentic Distillation $2K > 200h Real CoT Pass? Add CoT AST-Tree IR LLM-API Abandoned IR-Based Conversion Free < 2h Unreal CoT Workflow Reuse Existing Verilog Data FSM Protocol + ÷× − Arithmetic ≈ 36K Contamination Filter ≈ 3.4K Category-Specific Augmentation Python Ref Model Data Web Search Figure 3: Hybrid data generation framework combining LLM-API distillation, IR-based conversion, and category- specific augmentation to produce the reference-model train- ing corpus. Category-specificaugmentation. The two pipelines above yield approx- imately 61K samples, sufficient in quantity but not in coverage. After training Qwen3.5-4B on this dataset and evaluating on VerilogEval, we find that most failures concentrate in three categories: finite-state machines, multi-cycle protocol blocks (e.g. counters and FIFOs), and bit-level arithmetic.We collect additional Verilog examples targeting these categories via web search, convert them with the IR-based conversion pipeline and apply a contamination filter to exclude any overlap with benchmark test cases.This adds approximately 3.4K targeted samples, shifting the three categories’ share from approximately 15% to 28% and strengthening the model on precisely the task types where it is weakest. 3 Experiments 3.1 Implementation Details We obtain ChipMATE by applying our two-stage training pipeline (subsection 2.3) to the Qwen3.5 [26] base model (4B and 9B). Stage 1 comprises single-agent SFT followed by single- agent RL, and Stage 2 performs multi-agent RL. For SFT, we use LLaMA-Factory [36] to fine-tune Qwen3.5. The Verilog agent is trained on the 87K-sample dataset released with QiMeng CodeV- R1 [37], and the Python agent is trained on 64.4K reference-model samples generated by our hybrid 6 Table 1: Pass@k(%) for Verilog generation on four benchmarks. Within each column,1st(Gold), 2nd(Silver), and3rd (Bronze) are highlighted. TypeModelSize VerilogEval v2 RTLLM v2 ChipBench-SC CVDP cid03 P@1P@5P@1P@5P@1P@5P@1P@5 Foundation Models GPT-4o–64.173.756.570.320.033.339.040.4 GPT-5.5–84.790.463.268.030.736.744.048.7 Claude Opus 4.7–86.990.464.868.031.346.742.847.9 DeepSeek Coder236B68.580.857.670.016.730.022.337.2 DeepSeek V41.6T67.380.158.866.018.036.721.534.6 DeepSeek R1671B77.584.764.775.826.740.027.742.1 Specialized Models CodeV-R1 (distill)7B65.275.257.271.913.326.726.242.1 CodeV-R17B68.878.268.0 78.230.040.026.843.3 Base Models Qwen3.5-4B4B41.760.934.349.76.710.011.813.9 Qwen3.5-9B9B48.566.636.157.813.320.013.321.5 ChipMATE-Verilog-4B4B67.471.868.074.626.733.324.739.2 ChipMATE-Agents-4B4B75.076.374.677.333.343.332.141.3 ChipMATE-Verilog-9B9B75.377.671.975.830.036.728.142.1 ChipMATE (Ours) ChipMATE-Agents-9B9B80.182.475.877.336.743.340.444.6 framework (subsection 2.4). Both agents are trained for 6 epochs with a learning rate of1×10 −5 , a global batch size of 64, and a context length of 16,384 tokens. For single-agent RL, we use verl [23] with GRPO [22]. We set the global batch size and minibatch size to 128, the GRPO group size to 16, and the learning rate to1×10 −6 . Training runs for 300 steps with a rollout temperature of 1.0, an instruction length of 2,048, and a response length of 16,384. The reward function is the same local reward used in multi-agent RL. For multi-agent RL, we build on a modified version of PettingLLMs [34] with verl as the backbone. Both agents are updated for an additional 200 steps at the same learning rate. The 9B model is trained on two nodes of 8×H200 (141 GB each), and the 4B model on a single 8×H100 node. We evaluate ChipMATE on four widely used RTL generation benchmarks: VerilogEval v2 [19], RTLLM v2 [14], ChipBench-SC (the self-contained subset of ChipBench (78 cases) [32]), and CVDP cid03 [20]. The maximum context length is 16,384 tokens for all benchmarks. The generation temperature is set to 0.6 for the SFT-only checkpoint and 1.0 for the + RL and agentic checkpoints. We generate 10 responses per query and report pass@k [1] for k∈1, 5. 3.2 End-to-End Results Table 1 reports pass@kon the four benchmarks against large-scale foundation LLMs (GPT, Claude, and DeepSeek), hardware-specialized baselines (CodeV-R1 [37]), and open-source base models. The top-3 results in each column are highlighted with gold, silver, and bronze cells. Compared with the previous state-of-the-art self-trained model, QiMeng CodeV-R1, ChipMATE- Agents-9B achieves 6.7%–13.6% higher pass@1. Even the smaller ChipMATE-Agents-4B improves over CodeV-R1 by 3.3%–6.6% despite having fewer parameters (4B vs. 7B). When compared with state-of-the-art API-based LLMs that are 20–1000×larger, ChipMATE-Agents-9B outperforms all of them. The only comparable model is Claude Opus 4.7 and GPT-5.5, which achieves better performance on VerilogEval and CVDP but falls behind ChipMATE on RTLLM v2 and ChipBench. Notably, the gap between pass@5 and pass@1 for ChipMATE is considerably smaller than for other models. This is because the ChipMATE already self-corrects errors during inference, increasing the likelihood of producing correct code on the first attempt. This property aligns well with industrial needs, where pass@1 is the primary concern because chip design tolerates very few bugs. 7 Table 2: Pass@kaccuracy (%) of the Python reference-model track on four hardware-code benchmarks. Within each column,1st,2nd, and3rdare highlighted (ties share a rank). ChipMate- Python (ours) rows are shaded. TypeModelSize VerilogEval v2 RTLLM v2 ChipBench-SC CVDP cid03 P@1P@5P@1P@5P@1P@5P@1P@5 Foundation Models GPT-5.5– 61.575.548.555.433.042.141.647.4 DeepSeek Coder236B60.173.142.450.028.740.021.535.1 DeepSeek V41.6T59.771.844.454.330.740.024.736.5 DeepSeek R1671B57.170.7 49.657.828.736.726.237.2 Specialized Models CodeV-R1 (distill)7B40.448.536.046.223.330.024.737.2 CodeV-R17B45.356.442.751.828.733.322.334.6 Base Models Qwen3.5-4B4B46.863.738.246.116.723.310.212.7 Qwen3.5-9B9B48.064.740.151.820.026.711.419.9 ChipMate-Python-4B4B77.680.175.380.141.346.734.245.3 ChipMate-P (Ours) ChipMate-Python-9B9B82.484.777.381.043.350.043.346.7 3.3 Python Reference Model Generation Table 2 reports the results for Python reference-model generation. ChipMATE-Python-9B and ChipMATE-Python-4B both rank among the top two across all benchmarks, which we attribute to the quality of our synthetic dataset and training pipeline. Simulating hardware behaviour in Python is a fundamentally different task from general-purpose Python programming, and dedicated supervision turns out to be essential. Notably, ChipMATE-Python-9B achieves 5.4–15.2% higher pass@1 on the Python track than ChipMATE-Verilog-9B does on the Verilog track across all four benchmarks (+7.1% on VerilogEval v2, +5.4% on RTLLM v2, +13.3% on ChipBench-SC, and +15.2% on CVDP). This suggests that LLMs can readily leverage pre-trained Python priors once they receive targeted fine-tuning on hardware-behaviour simulation, which is precisely what our dataset and pipeline are designed to provide. Interestingly, foundation models such as DeepSeek score lower on the Python reference-model task than on direct Verilog generation. Given their well-established strength in general Python coding, we believe even lightweight fine-tuning on reference-model generation could substantially improve their hardware-design performance. 3.4 Python vs. Verilog To understand how our multi-agent workflow improves Verilog generation, we compare the three ChipMATE-4B variants in Figure 4. The Python agent consistently achieves the highest accuracy while the Verilog agent shows the lowest, with the multi-agent workflow landing between the two across all benchmarks. This indicates that the workflow effectively lifts Verilog generation quality toward the level of the stronger Python agent. It also highlights the critical role of reference-model generation: its accuracy sets the upper bound for the entire multi-agent workflow, yet this task has been largely overlooked by prior work. 3.5 Ablation Study Figure 5 presents the ablation study on VerilogEval v2 pass@1, tracing the contribution of each technique and training stage. Among all stages, SFT yields the largest gain (+19.2% on 4B, +22.0% on 9B), as it equips the LLMs with foundational Verilog generation knowledge. Single-agent RL and multi-agent RL then contribute a further 1.4%–6.5% improvement. Notably, simply applying a multi-agent workflow without backtracking leads to an unexpected drop of 11.6%–14.3%. We attribute this to the fact that neither agent produces perfect code, and 8 pass@1pass@5 65 70 75 80 Accuracy (%) VerilogEval v2 67.4 71.8 75.0 76.3 77.6 80.1 pass@1pass@5 70 75 80 RTLLM v2 68.0 74.674.6 77.3 75.3 80.1 pass@1pass@5 30 40 50 ChipBench-SC 26.7 33.333.3 43.3 41.3 46.7 pass@1pass@5 30 40 CVDP cid03 24.7 39.2 32.1 41.3 34.2 45.3 Verilog onlyAgents (combined)Python only Figure 4: Pass@kof different variant of ChipMATE-4B. The agentic workflow consistently lands between the two single agents. Base Base + SFT Base + SFT + RL Agents (w/o BT) Agents Agents + MA-RL 40 50 60 70 80 90 VerilogEval v2 pass@1 (%) Single-agent training Two-agent inference Multi-agent RL training ChipMATE-4B ChipMATE-9B 41.7 60.9 67.4 55.8 71.8 75.0 48.5 70.5 74.4 60.1 78.7 80.1 Figure 5: Ablation study on VerilogEval v2 pass@1, showing the contribution of each tech- nique and training step. (BT: Backtracking) T=1T=2T=3T=4 T=5 Cross-verification turns Best-of-1 Best-of-2 Best-of-3 Best-of-4 Best-of-5 Per-turn pairing strategy 70.573.175.075.675.0 71.273.774.475.075.6 73.174.475.675.075.0 71.874.475.075.074.4 71.873.173.774.473.7 70 72 74 76 pass@1 (%) Figure 6: Exploration of multi-agent parameters using ChipMATE-4B on VerilogEval pass@1. The combination of 3 turns and 3 samples is optimal. naively accepting every intermediate result causes severe error propagation. Once the backtracking mechanism is introduced, however, performance rebounds by 16%–18.6%, surpassing the single- agent result by 4.3%–4.4% and demonstrating the effectiveness of multi-agent collaboration. 3.6 Exploration of the Agentic Workflow We finally study the design space of the agentic workflow by fixing the ChipMATE-4B checkpoint and sweeping the per-turn sampling budget (Best-of-N,N∈1,..., 5) and the maximum number of turns (T ∈1,..., 5). As shown in Figure 6, accuracy does not increase monotonically with either factor, and a moderate setting ofN = 3,T = 3achieves the best result (75.6 pass@1). We therefore adopt Best-of-3,T = 3as the default configuration, as it reaches the peak accuracy at minimal inference cost. 4 Related Work API-based agentic Verilog generation. A large body of work improves RTL generation by wrapping frontier closed-source models in agentic workflows [27,8,11,17,9,21,30]. MAGE [35] decomposes the pipeline into specialized agents for the testbench generation, candidate sampling, and state-checkpoint debugging. VerilogCoder [8] further adds graph-based task planning and AST-driven waveform analysis. All of these systems require continuous access to proprietary API endpoints, conflicting with the security posture of chip vendors that air-gap core design servers, and offer no path to training on a company’s internal RTL codebase. Self-trained models for RTL generation. A parallel line trains locally deployable models via supervised fine-tuning (RTLCoder [13], AutoVCoder [5], BetterV [18], OriGen [7], CraftRTL [12]) 9 or reinforcement learning with verifiable rewards (VeriReason [28], RTLSeek [33], ChipSeek-R1 [4]). QiMeng-CodeV-R1 [37] combines rule-based testbench generation, round-trip data synthesis, and adaptive DAPO to train a strong local Verilog model. RTLSeek [33] optimizes design correctness and diversity through multi-stage diversity-oriented RL. These works address the deployment limitations of API-based systems but all rely on a golden testbench or reference implementation as an oracle, and model only the design engineer’s role. Concurrent to our work, SiliconMind-V1 [2] locally deploys a self-trained multi-agent workflow for Verilog generation. ChipMATE differs in that it trains two independent models (Verilog and Python reference-model agents) and develops dedicated training data for reference-model generation, a task where even 671B frontier models achieve below 20% pass@1, enabling code-blind cross-verification that mirrors industrial design-verification practice. 5 Conclusion We presented ChipMATE, a self-trained multi-agent framework for RTL code generation that supports fully offline deployment. ChipMATE pairs a Verilog agent with a Python reference-model agent that cross-verify outputs without any golden testbench or cloud-LLM API. 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A Agent Prompt Templates We list the system and user-message templates used by the Verilog agent and the Python reference- model agent during single-turn SFT and multi-agent rollouts, together with the retry-and-fix prompt fragments that X-GRPO injects on turnst>0whenever a V/P mismatch is detected. Both agents share a unified <think>...</think><answer>...</answer> reasoning format. A.1 Verilog Agent System Prompt Verilog agent system prompt You are a helpful assistant. The assistant first thinks about the reasoning process in the mind and then provides the user with the answer. The reasoning process and answer are enclosed within <think> </think> and <answer> </answer> tags, respectively, i.e., <think> reasoning process here </think><answer> answer here </answer>. Now the user asks you to write verilog code. After thinking, when you finally reach a conclusion, enclose the final verilog code in “‘verilog “‘ within <answer> </answer> tags. i.e., <answer> “‘verilog module top_module(in, out, ...) ... “‘ </answer>. 12 Example user message. The user message gives the natural-language behaviour and a structured port list (no Verilog code skeleton—only the interface): Example user message (Verilog agent, VerilogEval-style) I would like you to implement a module named TopModule with the following interface. All input and output ports are one bit unless otherwise specified. - input in (3 bits) - output out (2 bits) The module should implement a "population count" circuit that counts the number of ’1’s in the input vector. A.2 Python Reference-Model Agent System Prompt The Python agent operates in a skeleton-completion mode: the user message contains a natural- language spec plus a Python class skeleton that pins the class name, method signature, and exact signal names / bit-widths. The agent must complete the bodies of__init__andevalwithout renaming any identifier so that the cross-language verifier can drive the resulting class identically to the Verilog DUT. Python reference-model agent system prompt You are an expert hardware modeling assistant. Your task is to write Python code that serves as a cycle-accurate reference model for a Verilog hardware module. Your Python code’s outputs must match the expected outputs of the Verilog circuit exactly. The user will provide a natural language description of the module’s behavior and a Python code skeleton. You must complete the provided skeleton. Do not rename the class, method, or any signals. Use the exact signal names and bit-widths from the skeleton. GENERAL RULES: - Use bitwise operators: & | ~ » «. Each eval() call = one rising clock edge. Never read clk. - Mask all outputs and state variables to their correct bit-width, e.g. val & ((1 « N) - 1). FOR COMBINATIONAL CIRCUITS (no reset, no state): - Compute outputs directly from inputs in eval(). No state variables needed. FOR SEQUENTIAL CIRCUITS (has reset and/or state): - Declare all state variables in __init__(), initialized to 0. - In eval(): if reset is asserted, set all state and outputs to 0 and return. - Otherwise: compute next-state from current state (self.*) and inputs, compute outputs, then update self.* at the end. First, think step-by-step inside <think> </think> tags. Then, provide your final Python code inside <answer> </answer> tags with “‘python “‘ markers. Example user message (with skeleton). The user prompt injects the spec, a signal table, and a pre-populatedclass TopModuleskeleton in which the state variables and the input bit-masks are already laid out; the agent only fills in the sequential / combinational logic and the output expression. Example user message (Python agent, 3-stage pipelined ALU) Design a pipelined ALU that performs a sequence of arithmetic operations in three stages. The ALU should take four 10-bit inputs (a, b, c, d) and two clock signals (clk1, clk2) and produce a 10-bit output (F). The operations are as follows: 1. Stage 1: Compute a + b and c - d, and store the value of d. 13 2. Stage 2: Compute the sum of the results from Stage 1. 3. Stage 3: Compute the product of the result from Stage 2 and the stored value of d. The ALU should use pipelining to ensure that each stage operates independently, and the final result should be available at the output F. This Python class, named alu_op, has the interface designed in a port table (signal name, direction, width, description) for each of a, b, c, d, clk1, clk2, and F. Complete this skeleton: “‘python class TopModule: def __init__(self): self.stage1_d = 0 self.stage1_diff = 0 self.stage1_sum = 0 self.stage2_sum = 0 self.stage3_product = 0 def eval(self, inputs: dict) -> dict: a = inputs.get("a", 0) & 0x3F b = inputs.get("b", 0) & 0x3F c = inputs.get("c", 0) & 0x3F d = inputs.get("d", 0) & 0x3F # TODO: implement sequential logic return "F": ... “‘ Answer: A.3 Retry-and-Fix Prompt Fragments (X-GRPO turns t>0) When the previous turn’s V/P pair produced any mismatch on the random-stimuli cross-verification, X-GRPO appends three fragments to the user message of the next turn for the chosen best pair: previous code attempts (previous_code), the diff log (previous_error_log), and a one- sentence refinement instruction (refine_instr). Ont=0all three are empty strings, recovering the single-turn behaviour shown above. We display the Verilog-side fragments; the Python-side is structurally identical (substitute verilog→python, module code→class TopModule, //→#). (a) Previous-code fragmentprevious_code.The two most recent valid attempts (truncated to 1500 chars each) are re-injected so the agent can see its own trajectory: Previous-code fragment (Verilog side) Your previous Verilog attempts: Attempt k−1: “‘verilog <truncated previous code,≤ 1500 chars> // ...(code truncated)... “‘ Attempt k: “‘verilog <truncated previous code,≤ 1500 chars> // ...(code truncated)... “‘ (b) Verification-error fragmentprevious_error_log.A structured diff of the cross-verifier’s per-stimulus mismatches (truncated to 2000 chars). Crucially, the message frames the disagreement as mutual: the agent is told its peer might be the one at fault, preventing the V agent from over-correcting when the Python reference is actually wrong. 14 Verification-error fragment (Verilog side) Previous verification error: Verilog vs Python: m/N mismatches across T test vectors. First mismatches (got = your Verilog, exp = peer Python): Test 0, signal ‘out’: got=42, exp=37 (inputs: a=5, b=3, clk=1) Test 4, signal ‘out’: got=12, exp=8 (inputs: a=2, b=6, clk=1) ...(up to 5 mismatches shown)... Check your logic carefully. Either you or the Python agent is wrong –- only change your code if you think your previous code is wrong. (c) Refinement instructionrefine_instr. A short, fixed instruction emitted only ont> 0 turns: Refinement instruction (Verilog side) Please refine your Verilog code to improve correctness and quality. You MUST output the complete module code in “‘verilog“‘ blocks. (Python side) Please refine your Python code based on the mismatch feedback above. Output complete class TopModule in “‘python“‘ blocks. 15