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Self-Calibrating LLM-Based Analog Circuit Sizing with Interpretable Design Equations
Antonio J. Bujana, Aydin I. Karsilayan
Intelligence
Status: succeeded | Model: google/gemini-3.1-flash-lite-preview | Prompt: intel-v1 | Confidence: 95%
Last extracted: 4/10/2026, 3:41:20 AM
Summary
The paper introduces a self-calibrating framework for analog circuit sizing that uses an LLM to derive topology-specific analytical design equations from raw netlists. Unlike black-box optimization methods, this approach generates interpretable Python sizing functions. A deterministic calibration loop extracts process-dependent parameters from a single DC operating point simulation, allowing the framework to achieve convergence across different process nodes (180 nm and 40 nm) without retraining or per-process characterization.
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LLM-Based Analog Circuit Sizing → supportsprocessnode → 180 nm CMOS
confidence 95% · spanning three families at two process nodes (180 nm and 40 nm CMOS)
LLM-Based Analog Circuit Sizing → usessimulator → Spectre
confidence 95% · These are simulated in Cadence Virtuoso using the Spectre circuit simulator
LLM-Based Analog Circuit Sizing → validatedon → Operational Transconductance Amplifier
confidence 95% · We validate the framework on six operational transconductance amplifier (OTA) topologies
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Abstract
Abstract:We present a self-calibrating framework for analog circuit sizing in which a large language model (LLM) derives topology-specific analytical design equations directly from a raw circuit netlist. Unlike existing AI-driven sizing methods where the model proposes parameter adjustments or reduces a search space, the LLM produces a complete Python sizing function tracing each device dimension to a specific performance constraint. A deterministic calibration loop extracts process-dependent parameters from a single transistor-level simulation, while a prediction-error feedback mechanism compensates for analytical inaccuracies. We validate the framework on six operational transconductance amplifier (OTA) topologies spanning three families at two process nodes (180 nm and 40 nm CMOS). All 12 topology-node combinations achieve all specifications, converging in 2-9 simulations for 11 of 12 cases, with one outlier requiring 16 simulations due to an extremely narrow feasible region. Despite large initial prediction errors, convergence depends on the measurement-feedback architecture, not prediction accuracy. This one-shot calibration automatically captures process-dependent variations, enabling cross-node portability without modification, retraining, or per-process characterization.
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- Source: https://arxiv.org/abs/2604.07387v1
- Canonical: https://arxiv.org/abs/2604.07387v1
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1 * This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible. Self-Calibrating LLM-Based Analog Circuit Sizing with Interpretable Design Equations * Antonio J. Bujana 1 2 , Graduate Student Member, IEEE, and Aydin I. Karsilayan 1 , Member, IEEE Abstract—We present a self-calibrating framework for analog circuit sizing in which a large language model (LLM) derives topology-specific analytical design equations directly from a raw circuit netlist. Unlike existing AI-driven sizing methods where the model proposes parameter adjustments or reduces a search space, the LLM produces a complete Python sizing function tracing each device dimension to a specific performance constraint. A deterministic calibration loop extracts process- dependent parameters from a single transistor-level simulation, while a prediction-error feedback mechanism compensates for analytical inaccuracies. We validate the framework on six operational transconductance amplifier (OTA) topologies spanning three families at two process nodes (180 nm and 40 nm CMOS). All 12 topology–node combinations achieve all specifications, converging in 2–9 simulations for 11 of 12 cases, with one outlier requiring 16 simulations due to an extremely narrow feasible region. Despite large initial prediction errors, convergence depends on the measurement-feedback architecture, not prediction accuracy. This one-shot calibration automatically captures process-dependent variations, enabling cross-node portability without modification, retraining, or per-process characterization. Index Terms—AI-driven design automation, analog circuit sizing, large language model (LLM), operational transconductance amplifier (OTA), self-calibration, interpretable design equations. I. INTRODUCTION NALOG circuit sizing remains a labor-intensive task requiring expert knowledge to navigate complex tradeoffs between gain, bandwidth (gain-bandwidth product, GBW), phase margin (PM), and slew rate (SR). Despite decades of research into automated sizing — spanning optimization-based, knowledge-based, and large language model (LLM)-based methods (reviewed in Section I) — to the authors’ knowledge, no existing approach produces executable, topology-specific design equations directly from raw circuit netlists, and no prior work provides quantitative analysis of how prediction accuracy relates to convergence. This paper introduces a fundamentally different role for the LLM: deriving the analytical design equations themselves. The LLM receives a raw circuit netlist and produces a complete Python sizing function (compute_sizing()) encoding topology-specific equations — equations consistent with standard analog design theory, but generated 1 Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA. 2 Department of Engineering, Benedictine College, Atchison, KS, USA. Correspondence to: A. J. Bujana tonybujana@tamu.edu automatically from the netlist. A deterministic calibration loop then anchors these equations in process-accurate simulation data by extracting process-dependent parameters from a single DC operating point (OP) simulation. The key insight is that LLM-generated equations need only be structurally correct — even if their numerical predictions are inaccurate. We define structural correctness as the property that the equations (i) correctly identify which devices govern each specification, (i) correctly capture the direction of each device's influence, and (i) correctly represent how specifications trade off against each other through shared devices. Structural correctness is essential: it ensures that the prediction-error feedback drives the design toward convergence rather than oscillation. When a specification falls short, structurally correct equations direct the LLM to adjust the right devices in the right direction, even if the quantitative adjustment is imprecise. The calibration loop corrects numerical errors, and the prediction-error feedback compensates for systematic analytical inaccuracies that persist after calibration. The main contributions of this work are as follows: 1) An end-to-end, self-calibrating sizing workflow — validated across six operational transconductance amplifier (OTA) topologies spanning three families at two process nodes (180 nm, 40 nm). Unlike existing LLM-based sizing approaches that produce only final device dimensions, this framework preserves calibrated, human-readable design equations — commented Python code tracing each device dimension to a specific performance constraint. The only per-circuit inputs are the netlist, target specifications, and supply voltages; all scripts and prompt templates are shared across topologies and nodes with no modification. 2) A calibration feedback architecture that decouples convergence from the LLM's numerical prediction accuracy. The LLM-derived equations must be structurally correct — correctly mapping specifications to governing devices and influence directions — but need not be numerically accurate. Quantitative prediction-error analysis across 78 simulation rounds at two process nodes confirms this decoupling (Section V- B). 3) Cross-node portability via self-calibration. The one-shot DC OP extraction automatically captures process- dependent parameters (μC ox , αg m , λ, V th ) that vary significantly between 180 nm and 40 nm, enabling the same framework to self-calibrate without modification, per-process characterization data, or retraining. 4) Empirical analysis of topology-dependent convergence difficulty across two process nodes, including A 2 identification of a narrow feasible region case (PMOS- input folded cascode at 180 nm) requiring 16 simulations, analyzed in Section V-D. I. PRIOR WORK Existing automated sizing approaches fall into three broad categories: optimization-based methods that treat the circuit as a black box, knowledge-based methods that rely on pre- characterized device data, and LLM-based methods that leverage language models in various roles. Each is reviewed below. A. Optimization-Based Methods Black-box optimization methods formulate circuit sizing as a numerical optimization problem. Bayesian optimization (BO) [1] uses Gaussian process surrogates to efficiently explore the design space. Traditional implementations require hundreds to thousands of simulations to converge, though recent work on initialization strategies [2] has substantially reduced this for OTA-class circuits — including two-stage Miller-compensated, folded cascode, and telescopic cascode topologies at 45 nm CMOS — achieving design closure in as few as 21 total simulations. Two of these three circuit families (two-stage Miller, folded cascode) overlap with the topologies validated in this work, enabling qualitative comparison between BO-based and LLM-based approaches on the same circuit class (Section VI-C). Geometric programming [3] achieves faster convergence through convex formulations but requires the designer to manually construct posynomial models for each topology. Reinforcement learning methods [4] train agents through simulation rewards but require per- topology training episodes and produce no analytical insight. These methods achieve good performance but treat the circuit as a black box — the final sizing comes with no interpretable rationale explaining why specific dimensions were chosen. B. Knowledge-Based Methods The g m /I D methodology [5] represents the most widely adopted knowledge-based approach. It uses pre-characterized lookup tables relating transconductance efficiency to inversion level, enabling systematic operating-point selection. However, it requires per-process characterization sweeps (typically W and L sweeps across the full operating range), and a human expert must interpret efficiency curves, select operating points, and manually derive the design equations linking specifications to device dimensions. These two requirements — manual equation derivation and per-process characterization — represent the primary bottlenecks of the g m /I D approach. C. LLM-Based Sizing Methods The landscape of LLM-based analog sizing methods has expanded rapidly. These approaches can be categorized by the role assigned to the LLM. 1) LLM as optimizer: EEsizer [6] uses an LLM directly to propose sizing adjustments based on simulation feedback. The LLM analyzes performance gaps and suggests parameter changes iteratively. Testing across eight LLMs on basic circuits, the authors scaled to a 20-transistor opamp and demonstrated cross-node applicability across 180 nm, 130 nm, and 90 nm, achieving target specifications across multiple test groups. The approach relies on the LLM's ability to propose good parameter adjustments — a capability that varies significantly across models and topologies. 2) LLM as search-space guide: LEDRO [7] uses an LLM to iteratively reduce the design search space for a TuRBO optimizer. By having the LLM propose refined parameter ranges based on simulation feedback, LEDRO reduces the exploration complexity for the downstream optimizer. Tested on 22 op-amp topologies across four FinFET nodes, it demonstrates broad generalizability. However, convergence ultimately depends on the TuRBO optimizer, and the LLM's role is limited to search-space pruning rather than analytical reasoning about circuit behavior. 3) LLM as knowledge transfer agent: LLM-USO [8] introduces structured knowledge representations encoding relationships between performance metrics, circuit sub- structures, and sizing parameters. This enables transfer learning across circuits with similar sub-structures via a knowledge summary mechanism, mirroring expert designers' ability to reuse insights. ADO-LLM [9] combines in-context learning with BO, using the LLM to propose promising design points within a BO framework. 4) LLM as multi-agent system: AnaFlow [10] employs specialized LLM agents that collaborate in a multi-agent workflow, providing structured reasoning and explainability. Atelier [11] extends this with a graph-of-thoughts architecture integrating a curated knowledge base, achieving superior performance over black-box methods on specific topologies. AutoSizer [12] introduces a reflective meta-optimization framework where LLM agents adaptively select and configure optimization algorithms within a two-loop architecture, tested on 24 circuits including oscillators, switched-capacitor circuits, and filters. TopoSizing [13] performs circuit understanding from raw netlists using graph algorithms to organize circuits into hierarchical device–module–stage representations, then uses LLM agents in a hypothesis- verification loop to produce annotations that guide BO. While TopoSizing produces structured circuit annotations, it does not derive executable analytical sizing equations. 5) Lightweight and cross-node methods: EasySize [14] fine- tunes a lightweight Qwen3-8B model for cross-node applicability, achieving strong performance at 180 nm, 45 nm, and 22 nm nodes despite training only on 350 nm data. LLMACD [15] operates in transistor behavioral-parameter space, using a behavioral model to map LLM-generated parameters to device sizes with manually embedded design knowledge. AmpAgent [16] uses literature retrieval to port amplifier designs across processes and performance targets. 3 I. PROPOSED METHODOLOGY Despite the breadth of existing approaches (Section I), LLM-based sizing methods share a common architectural pattern: the LLM serves as either an optimizer — suggesting parameter adjustments based on simulation feedback — or a search-space guide that reduces the region for a downstream optimizer. Table I positions the proposed framework against these methods; the key differentiators are detailed in the contributions (Section I). Existing methods that claim explainability (AnaFlow, Atelier) provide reasoning traces explaining why the LLM made specific parameter adjustments — valuable for understanding the optimization trajectory, but not equivalent to calibrated design equations. TopoSizing [13] produces structured annotations but uses them to guide BO rather than deriving executable sizing equations. The proposed framework outputs a complete sizing function where each line of code maps a specification to device dimensions through explicit analytical relationships. This provides two distinct advantages beyond explainability. First, traceability for design review: before committing to layout, a designer can inspect which specification constrained each device dimension — a property valued in production design flows that black-box methods cannot provide. Second, diagnostic transparency: when convergence is slow or a specification is marginal, the calibrated equations identify whether the root cause is a parametric error (e.g., inaccurate μC ox ) or a fundamental topological limitation (e.g., the topology cannot simultaneously meet all specifications at the given supply voltage). As discussed in Section VI-A, the equations also provide the LLM with a causal model of the circuit that anchors its sizing adjustments across rounds — ensuring convergent rather than oscillatory behavior. A. Framework Overview The proposed framework operates in iterative rounds, as shown in Fig. 1. Each round comprises four steps: prompt assembly, LLM equation generation or update, sizing execution, and simulation with calibration. 1) Round 0: A prompt-assembly script (build_prompt.py) combines the circuit netlist, target specifications, constraint rules, and a structured template into a single prompt. The LLM receives this prompt and produces two outputs: (i) initial estimates of process-dependent device parameters for every transistor (μC ox , αg m , λ, V th ), informed by device constraints specified in the netlist, and (i) a Python sizing function, compute_sizing(), encoding the topology's design equations. This task requires the LLM to interpret the raw netlist — recognizing the circuit topology, identifying device roles and signal paths, and deriving structurally correct design equations directly from the netlist. While the calibration feedback architecture is model-agnostic in principle, the framework's effectiveness depends on the LLM’s netlist-interpretation capability. A deterministic script (solve.py) executes the sizing function using the LLM's parameter estimates, producing design variables (W, L, bias currents, etc). These are simulated in Cadence Virtuoso using the Spectre circuit simulator: stability analysis (STB) extracts the voltage gain (A v ), GBW, and PM from the loop-gain response; transient analysis with a large-signal step input extracts SR+ and SR−; and DC OP analysis extracts per- device g m , g ds , V th , I d , V gs , and V ds . Finally, a calibration script (calibrate.py) processes the simulation results: it extracts TABLE I COMPARISON WITH EXISTING METHODS Method LLM Role Interpretable Equations Pre-characterization Cross-Node Prediction-Error Analysis BO [1] None No (black box) None Re-run required * N/A BO-Init [2] None No (black box) Initial samples (16+) Not demonstrated (45 nm only) No g m /I D [5] None Partial (efficiency curves) Lookup tables Manual porting N/A EEsizer [6] Optimizer No None Yes (3 nodes) No LEDRO [7] Search-space guide No None Yes (4 nodes) No LLM-USO [8] Knowledge transfer No None Not specified No AnaFlow [10] Multi-agent Partial (reasoning traces) None Not demonstrated (45 nm only) No Atelier [11] Multi-agent + KB Partial Knowledge base Yes (2 nodes) No AutoSizer [12] Meta-optimizer No None Not demonstrated (130 nm only) No TopoSizing [13] Circuit understanding Partial (annotations) None Not demonstrated (55 nm only) No EasySize [14] Fine-tuned optimizer No Training data (350nm) Yes (3 nodes) † No This work Equation derivation Yes (Python code) None (self-calibrating) Yes (2 nodes) Yes (78 rounds) * ‘Re-run required’ indicates the method must be re-executed from scratch at each new node † Trained on 350 nm; tested at 180 nm, 45 nm, and 22 nm nodes. 4 four calibration parameters per device from the DC OP, computes predicted-versus-actual performance, and assembles the Round 1 prompt. 2) Round N ≥ 1: The LLM receives the prompt assembled by the previous round's calibration output and generates only an updated sizing function — it does not re-estimate device parameters, as these are now provided by calibrate.py's simulation-extracted values. The updated function is executed by solve.py, Cadence simulates, and calibrate.py extracts updated parameters and assembles the next prompt. The loop completes when all specifications are met. B. One-Shot Calibration The calibration extracts device-level parameters from a single DC OP simulation. No additional test structures, characterization sweeps, or lookup tables are required. For each transistor in the circuit, calibrate.py computes four parameters. 1) Effective transconductance parameter μC ox (A/V²): Derived from the saturation current equation I d = ½·μC ox ·(W/L)·V ov ², where V ov = V gs − V th is the overdrive voltage. This captures the combined effect of carrier mobility, oxide capacitance, and mobility degradation at the actual operating point. 2) Transconductance non-ideality factor αg m : The ratio of actual g m to the ideal value 2·I d /V ov . This factor accounts for velocity saturation and short-channel effects that reduce g m below the long-channel prediction. In the tested processes, αg m is typically below 1.0, depending on device type, channel length, and overdrive voltage. 3) Channel-length modulation coefficient λ (1/V): Computed as g ds /I d , where g ds is the output conductance from the OP. This parameter varies significantly with channel length and is critical for determining output resistance and voltage gain. 4) Threshold voltage V th (V): Extracted directly from the OP, including body-effect shifts for devices with non- grounded source terminals. These four parameters capture the dominant process- specific effects — velocity saturation, channel-length modulation variation with L, body-effect threshold shifts, and mobility degradation — that vary significantly between process nodes. The one-shot extraction automatically adapts to the process node without modification to the calibration scripts. Since these parameters depend on the device's operating point (which changes as W, L, and bias currents are adjusted each round), calibrate.py re-extracts all four parameters from every simulation, providing the LLM with updated values that reflect the current sizing. The operating-point dependence of the extracted parameters is substantial. Table I shows representative calibration data for the differential-pair input device (M1) sampled across different topologies, process nodes, and rounds. These samples were drawn from different points in the design space and illustrate three key observations. First, μC ox varies by 2.9× (1,614 to 4,710 μA/V²) among NMOS devices at the same node and channel length (40 nm, L = 0.20 μm), driven by operating-point differences. Second, for the same topology and device between rounds (2SMC-P at 180 nm, R5 vs. R8), μC ox shifts by 2.1× (211 to 98 μA/V²) as the sizing evolves, confirming the necessity of per-round re- extraction. Third, αg m is below 1.0 in all Table I entries, varying from 0.21 to 0.79 — a 3.8× range — consistent with actual transconductance falling well below the ideal long- channel value at both nodes. The calibration data is presented to the LLM in a structured per-device table (Fig. 2) that includes the device type, W/L, measured current, overdrive voltage, transconductance, saturation status, and all four extracted parameters. The table also flags devices operating in the triode region (|V ds | < V ov ), which alerts the LLM to bias-point failures requiring correction in the next round. build_prompt.py LLM: Claude (Opus 4.6) •Sizing function: compute_sizing() •Initial estimate: 휇퐶 ox ,훼푔 m ,휆,푉 th (Round 0 only) Inputs: Circuit netlist, target specs, prompt template design rules START calibrate. py •Extract 휇퐶 ox ,훼푔 m ,휆,푉 th •Compute predicted vs measured error •Assemble next -round prompt Specs met? Cadence Virtuoso / Spectre •STB: 퐴 v ,GBW,PM ,SR •Transient: SR+, SR- •DC OP per device 퐼 d ,푉 gs ,푉 ds ,푔 m ,푔 ds ,푉 th Design variables 푊,퐿,퐼 푏푖푎푠 ... solve.py •Executes sizing function •Outputs design variables Round 0 Prompt END Yes No Round N Prompt TABLE I CALIBRATION PARAMETER VARIATION (DEVICE M1) Topology Node Round Type L (μm) V ov (mV) μC ox (μA/V²) αg m λ (1/V) 2SMC-N 40nm R0 NMOS 0.2 49 1614 0.36 0.64 CM-N 40nm R2 NMOS 0.2 43 1934 0.32 0.65 FC-N 40nm R5 NMOS 0.2 27 4710 0.21 0.56 2SMC-P 180nm R5 PMOS 0.3 44 211 0.36 0.31 2SMC-P 180nm R8 PMOS 0.3 89 98 0.58 0.26 FC-P 180nm R8 PMOS 0.5 178 64 0.79 0.08 Fig. 1. Self-calibrating framework architecture. The loop iterates until all target specifications are met. 5 C. Prediction-Error Feedback After each simulation round, calibrate.py computes the discrepancy between the LLM's predicted performance and the Cadence-measured results. The next-round prompt presents a side-by-side comparison and includes metric-type-specific margin formulas embedded directly in the prompt text. For linear metrics (GBW, SR), the instruction reads: "if over- predicted by X%, design for (1 + X/100) × target." For logarithmic metrics (A v in dB): "if over-predicted by Y dB, design for target + Y dB." For phase margin: additive degree margin — “if over-predicted by Z°, design for target + Z°." These are explicit, formulaic instructions — not vague guidance — enabling the LLM to compute corrected design targets arithmetically. A cumulative historical log of all prior rounds is included, enabling the LLM to identify persistent prediction biases and distinguish between parametric errors (which shrink with calibration) and analytical model errors (which persist across rounds). The prediction-error feedback also includes targeted diagnostic guidance derived from failure modes observed during framework development. For example, a PM prediction exception instructs the LLM that if its predicted PM is catastrophically low but the Cadence-measured PM passes, the analytical PM equation is inaccurate and the LLM should trust the measured value rather than distorting the sizing to fix a prediction artifact. Such instructions encode domain knowledge about common analytical failure modes into the feedback loop; additional static constraints embedded in the prompt template are detailed in Section I-D. This feedback is critical because certain analytical inaccuracies — such as systematic GBW over-prediction caused by unmodeled parasitic capacitances — are inherent in the analytical model, not in the extracted parameters, and persist after calibration. The feedback compensates by instructing the LLM to add design margin proportional to the observed over-prediction. D. Structured Prompt Design The prompt enforces a multi-section output structure that requires the LLM to perform systematic topology analysis before writing any sizing code. The Round 0 prompt mandates seven sections in sequence: (1) Device Roles — labeling each transistor's function (e.g., "NMOS diff-pair input," "PMOS diode-connected active load") (2) Device Constraints — classifying each device (3) Signal Path — tracing the signal from input to output (4) Design Equations — deriving symbolic expressions for gain, bandwidth, slew rate, and compensation (5) DC Bias Verification — checking that all branch voltages support device saturation (6) DC OP Consistency — verifying numerical compatibility of inter-stage node voltages (7) Python Code with initial device estimates This forced decomposition prevents the LLM from jumping directly to code generation without first reasoning about the circuit structure — a failure mode observed during early development that produced syntactically correct but topologically wrong sizing functions. Within this structure, several specific constraints encode analog design knowledge that the LLM lacks. 1) Device classification rules require the LLM to label each transistor as MIRROR (sized by width ratio W/W ref relative to a reference device), MATCHED (identical W and L to a partner), or INDEPENDENT (sized directly by a performance equation). Each classification enforces a specific sizing formula in the Python code: mirror devices use W = W ref × I target /I ref × L/L ref , matched devices copy their partner's dimensions, and independent devices use the square- law equation W = 2·I d ·L / (μC ox ·V ov ²). Mirror devices must use the same channel length as their reference device, because V th depends on L in short-channel processes. Violating this constraint was observed to cause mirror current errors exceeding 50%. 2) An anti-circularity rule requires the LLM to compute inter-stage node voltages strictly from the driving stage's device parameters (e.g., V net5 = V D − V th,p − V ov,8 ), preventing circular reasoning in which the LLM assumes a bias point and then verifies it against itself. 3) DC OP consistency rules require the LLM to show explicit numerical computation at every constrained node, verifying that the voltage one stage produces is compatible with what the next stage requires. The prompt requires explicit arithmetic at every headroom check, prohibiting the LLM from making vague assertions such as 'self-adjusts' or 'consistent by construction’ without numerical verification. Dev Type W/L |Ids| VovVdsgm Region mu_Coxa_gmlam roVth (um/um) (uA) (mV) (mV) (uS) (uA/V2) (1/V) (kOhm) (mV) M1 NMOS 0.7/0 .20 6.97 49.0 526.4 101.37 SAT 1613.7 0.356 0.6368 225.2 438.2 M2 NMOS 0.7/0.20 7.22 55.6 435.3 103.12 SAT 1298.4 0.397 0.6756 204.9 438.2 M3 PMOS 1.3/0.20 6.97 68.7 517.4 89.24 SAT 447.8 0.440 0.4032 355.6 448.7 M4 PMOS 1.3/0.20 7.22 69.3 608.5 91.87 SAT 455.9 0.441 0.3745 369.5 448.1 M5 NMOS 2.0/0.20 14.20 83.0 56.2 145.49 TRIODE 404.1 0.425 12.9403 5.4 430.2 M6 NMOS 1.7/0.20 25.00 83.0 513.2 313.43 SAT 864.0 0.520 0.5812 68.8 430.2 M7 NMOS 4.8/0.20 72.68 83.0 543.4 907.97 SAT 879.1 0.518 0.5663 24.3 430.2 M8 PMOS 5.2/0.20 72.68 160.0 556.6 634.49 SAT 220.1 0.698 0.3326 41.4 448.5 WARNING: M5 in TRIODE (|Vds|=56mV < Vov=83mV) Fig. 2. Calibration table from calibrate.py output for 2SMC-N at 40 nm, as provided to the LLM in the Round 1 prompt. M5 is flagged as operating in the triode region. 6 4) A parasitic capacitance warning informs the LLM that large device widths create parasitic C gs and C db at internal nodes, degrading bandwidth and phase margin. The prompt instructs the LLM to consider reducing W through higher overdrive voltage as a first recourse before attempting other compensation adjustments. This single prompt addition resolved a systematic convergence failure observed during development in which the LLM's response to failing PM was to increase current or device widths, inadvertently worsening the problem. The LLM's output for each topology is a complete, commented Python function (compute_sizing()) that typically spans 200–300 lines. Fig. 3 shows a representative excerpt from the 2SMC-P 180 nm Round 0 output. Three features are notable: the LLM derives a joint GBW/SR constraint that selects the binding specification automatically, it applies all three device classification types (INDEPENDENT, MIRROR, MATCHED) with the correct sizing formula for each, and it cancels the RHP zero by setting R = 1/g m8 — all without human guidance. The framework requires no topology-specific prompt tuning. The prompt structure applies identically across circuits ranging from 8 transistors (two-stage Miller-compensated) to 18 transistors (folded cascode, current-mirror), and across process nodes from 180 nm to 40 nm. IV. EXPERIMENTAL SETUP A. Technology and Specifications Designs are validated at two process nodes, with target specifications shown in Target rows of Table I. 180 nm CMOS: V D = +0.9 V, V S = −0.9 V, C L = 1 pF. 40 nm CMOS: V D = +0.55 V, V S = −0.55 V, C L = 0.5 pF. The 40 nm technology supports higher operating frequencies due to shorter channel lengths and higher device f t , motivating the 2× higher GBW and SR targets. The gain target is reduced from 60 dB to 40 dB and C L from 1 pF to 0.5 pF to maintain comparable design difficulty; the reduced voltage headroom (1.1 V vs. 1.8 V) tightens the coupling between gain, bandwidth, and bias-point feasibility, while the higher GBW and SR targets demand greater transconductance and bias current under tighter headroom constraints. B. Topologies Tested Three OTA topology families are tested, each with NMOS- input and PMOS-input variants, yielding six topologies per node and 12 total. The NMOS-input variant of each family is shown in Fig. 4. The PMOS-input variants use the complementary device types with the same topology structure. All circuits are internally biased through current mirrors driven by a single ideal reference current source (I ref ). The two-stage Miller-compensated topologies also include an ideal compensation capacitor (C c ) and nulling resistor (R z ); the single-stage topologies (folded cascode, current-mirror) require no Miller compensation network. 1) Two-stage Miller-compensated (2SMC-N, 2SMC-P): 8 transistors plus a Miller compensation capacitor C c and nulling resistor Rz. The two-stage architecture decouples gain from bandwidth through the compensation network. 2) Current-mirror OTA with cascode output (CM-N, CM-P): 18 transistors in a single-stage topology where the gain mechanism relies on current-mirror amplification with cascode devices at the output for high output impedance. 3) Folded cascode (FC-N, FC-P): 18 transistors in a single- stage topology with cascode loads providing high output impedance. The folded cascode represents the most constrained topology due to tight coupling between gain, bandwidth, and phase margin in a single stage. Testing all three families with both polarities at two process nodes provides 12 independent validation points for the framework's generality across OTA families and cross-node claims. # --Current design: jointly set by GBW and SR -- # Relationship: SR_internal= 2*pi*GBW*Vov1 SR_internal_from_GBW= ( 2.0 * math.pi* GBW * Vov1) ifSR_internal_from_GBW>= SR_target : GBW_design= GBW # GBW-limited else: GBW_design= ( # SR-limited SR_target/ (2.0 * math.pi* Vov1)) Cc = 0.5e-12 gm1_target = 2.0 * math.pi* GBW _design* Cc Itail= gm1_target * Vov1 Id1 = Itail/ 2.0 # Second-stage current: output SR and PM Id2_SR = SR_target* CL gm8_for_fp2 = ( # fp2 >= 2.2*GBW 2.2 * GBW * 2.0 * math.pi* CL) Id2_fp2 = gm8_for_fp2 * Vov8 / 2.0 Id2 = max(Id2_SR, Id2_fp2) # --Device widths -- # M6: INDEPENDENT (PMOS ref, carries Iref) W6 = 2.0*Iref*L6 / (mu_Cox_p* Vov6**2) # M5: MIRROR of M 6, carries Itail W5 = W6 * (Itail / Iref) * ( L5 / L6) # M7: MIRROR of M6, carries Id2 W7 = W6 * (Id2 / Iref) * (L7 / L6) # M1, M2: MATCHED diff pair (each carries Id1) W1 = 2.0*Id1*L1 / (mu_Cox_p* Vov1**2) W2 = W1 # M8: INDEPENDENT (NMOS CS gain , carries Id2) W8 = 2.0*Id2*L8 / (mu_Cox_n* Vov8**2) # --Compensation (nulling RHP zero) -- gm8_sized, Vov8_v = calc_gm("M8", Id2, W8, L8) R = 1.0 / gm8_sized Fig. 3. Excerpt from the LLM-generated compute_sizing() function for 2SMC-P at 180 nm, Round 0. Each device dimension traces to a specific performance constraint through explicit analytical equations. The complete function (~200 lines) is executed unmodified. 7 C. Experimental Controls The following controls ensure reproducibility and prevent data contamination: Each LLM call uses a fresh session with no conversation history, as discussed in Section VI-B. Each topology is tested independently with no cross-topology learning. The LLM model is Claude Opus 4.6 (Anthropic), accessed through the claude.ai web interface. Only the structured prompt and calibration data are provided — no per-topology design hints, manual parameter adjustments, or iterative coaching. All compute_sizing() code generated by the LLM is executed unmodified. The Cadence testbench is identical across all topologies: unity-gain feedback with Spectre STB analysis, transient and DC OP analyses. Convergence is defined as simultaneously meeting all target specifications in a single simulation. Simulation counts in Table I include Round 0 (the initial sizing from LLM estimates); thus, a topology converging at Round N requires N + 1 total simulations. Each topology– node combination was tested in a single run. Due to the inherent non-determinism of LLM responses, round counts may vary across different runs; the reported results represent a single trial per combination and should be viewed as demonstrations of feasibility rather than expected performance. Practical deployment. The three deterministic scripts (build_prompt.py, solve.py, calibrate.py) are fully reproducible and execute in seconds. The non-deterministic component is the LLM's equation generation, which produces a ~300-line Python function per round. Each round requires one LLM call (~10,000 input tokens, ~5,000 output tokens) and one Cadence simulation (~30 seconds). The framework can be deployed with any LLM capable of interpreting circuit netlists and deriving governing design equations from them; the fresh- session architecture requires no persistent LLM state between rounds. The prompt templates, design-rule constraints, circuit netlists, and automation scripts (build_prompt.py, solve.py, calibrate.py, and Cadence OCEAN scripts) are available from the authors upon request. TABLE I CONVERGENCE RESULTS Topology Family Node Sims A v (dB) GBW (MHz) PM (°) SR+ (V/μs) SR− (V/μs) Target — 180nm — ≥ 60 ≥ 100 ≥ 60 ≥ 50 ≥ 50 2SMC-N Miller 180nm 6 60.4 101.3 74.8 97.2 83.5 2SMC-P Miller 180nm 3 64.5 139.4 65 70.4 170.4 CM-N Current mirror 180nm 2 61.8 115.6 60.2 95.1 99.7 CM-P Current mirror 180nm 4 64.4 118 64.5 63.3 106.8 FC-N Folded cascode 180nm 8 60.6 100.4 63.6 64.4 68.8 FC-P Folded cascode 180nm 16 60.2 102.3 60.1 100.1 82.5 Target — 40nm — ≥ 40 ≥ 200 ≥ 60 ≥ 100 ≥ 100 2SMC-N Miller 40nm 8 43.1 215.6 66.6 183.8 129.5 2SMC-P Miller 40nm 3 50.4 231.8 71.4 105.5 144 CM-N Current mirror 40nm 4 45.3 337.6 80 194.1 131.9 CM-P Current mirror 40nm 7 40.8 241.6 76.6 115.2 171.7 FC-N Folded cascode 40nm 9 44.1 302.1 66.6 107.2 137.2 FC-P Folded cascode 40nm 8 42.3 371.4 82.7 131.8 205 M1 M2 M3M4 M5 M6M7 M8 Cc Rz Iref VDD VSS Vi-Vi+ Vout (a) Two-stage Miller-compensated (2SMC-N) M1M2 Vi- Vi+ Vout M3 M 4 M7 M8 M5M6 M9M10M11 Iref M12M13 M14M16 M15M18 M17 VDD VSS Biasing Amplifier (c) Folded cascode (FC-N) M 1M2 Vi-Vi+ Vout M3M4M7M8 M9M10 M5 Iref M6M13 M14M16 M15M18 M17 VDD VSS M11 M12 Biasing Amplifier Fig. 4. Schematic diagrams of the three OTA families (NMOS-input variants shown) (b) Current-mirror (CM-N) 8 V. RESULTS A. Convergence Summary Table I presents convergence results for all 12 topology– node combinations, each meeting all target specifications. The per-round convergence trajectories are shown in Fig. 5 for 40 nm (left) and 180 nm (right), where dashed lines indicate target specifications. Of the 12 topology–node combinations, 11 converge in 2–9 simulations (median: 6.5). The CM-N at 180 nm converges fastest (2 simulations), while the FC-P at 180 nm is the sole outlier at 16 simulations — analyzed in Section V-D. At 40 nm, all six topologies converge within 3–9 simulations with no outlier, despite the LLM's substantially worse initial predictions at this node, as detailed below. B. Prediction Accuracy and Cross-Node Comparison The cross-node comparison reveals a pattern that directly supports a key claim of this work: convergence depends on the measurement-feedback architecture, not on prediction accuracy. Comparing the LLM’s predicted performance against Cadence-measured results, the initial predictions (Round 0) at 40 nm are substantially worse than at 180 nm across gain, GBW, and SR: gain over-predictions range from +23.7 to +57.6 dB (versus +11.3 to +34.4 dB at 180 nm). GBW over-predictions are far more severe: +168 to +469 MHz at 40 nm versus +6 to +61 MHz at 180 nm, with the worst case (CM-N at 40 nm) predicting 562 MHz against an actual 93 MHz — a 6.0× error. Slew rate over-predictions reach +188 V/μs at 40 nm (FC-N: predicted 200, actual 11.6 V/μs), compared to at most +24.8 V/μs at 180 nm. Despite this substantial degradation, all six 40 nm topologies converge within 3–9 simulations with no outlier — because the framework feeds back Spectre-measured performance, not the LLM's predictions, at every round. The decoupling also holds within each node: at 40 nm, CM-N has the largest Round 0 GBW error (+469 MHz) yet converges fastest (4 simulations), while 2SMC-N has the smallest gain error (+23.7 dB) yet requires 8 simulations. At 180 nm, the pattern is similar — CM-N converges in 2 simulations despite larger initial errors than 2SMC-N, which requires 6. Convergence speed correlates with topology- specific feasibility margins (Section V-D), not with initial prediction accuracy. C. Prediction Error Patterns Aggregating across all 78 simulation rounds spanning both process nodes, several systematic patterns emerge. 1) GBW is consistently over-predicted. GBW over-prediction occurs in 90% of all rounds (70 of 78), with a mean over- prediction of +87%. At 180 nm, mean GBW error is +32%; at 40 nm, it increases to +141%. The root cause is that the LLM's analytical GBW equation does not account for parasitic capacitances at internal nodes, which increase the effective load capacitance beyond C L . This is an analytical model error — it persists even after parametric calibration because parasitic capacitances are not among the extracted parameters. 2) Gain prediction improves dramatically after calibration. Round 0 gain errors range from +11 to +58 dB but reduce to within ±6 dB by the converging round at both nodes. This improvement reflects the effectiveness of the one-shot μC ox and λ calibration: the LLM's gain equations are structurally correct (correctly identifying the contributing g m and g ds terms), and once the parameters are calibrated, gain prediction becomes reasonably accurate. 3) SR prediction is topology-dependent and node-dependent. At 180 nm, SR prediction errors at Round 0 are moderate: over-predictions reach +24.8 V/μs (2SMC-P), while under- predictions reach -20.9 V/μs (FC-N). At 40 nm, Round 0 SR errors are much larger — up to +188 V/μs (FC-N: predicted 200, actual 11.6 V/μs). The dominant source of SR error is inaccurate bias-current estimation: before calibration, the LLM uses incorrect μC ox values to compute mirror ratios, leading to wrong tail and output-stage currents that directly set Fig. 5. Convergence trajectories of OTAs. The left and right columns correspond to 40 nm and 180 nm, respectively, while the rows show A v , GBW, PM, SR+, and SR-. Dashed lines indicate target specifications. 9 SR = I/C. A secondary contribution comes from unmodeled parasitics at internal nodes, which increase the effective capacitance being slewed. Some early rounds at 40 nm produce near-zero actual SR (e.g., FC-P R2: actual SR+ = 2.8 V/μs), indicating a nearly non-functional design that the framework subsequently corrects. 4) PM prediction errors are large but bidirectional. Unlike GBW, which is systematically over-predicted, PM errors show no consistent direction — the LLM over-predicts PM in some topologies and under-predicts in others, with errors persisting even at the converging round (e.g., +25.3° for 2SMC-N at 180 nm, −15.7° for 2SMC-N at 40 nm). This reflects the difficulty of analytical PM estimation: phase margin depends on the relative positions of multiple poles and zeros, each affected by the same unmodeled parasitics discussed above, making PM the least analytically predictable of the four metrics across the full design trajectory. D. Convergence Analysis: The FC-P 180 nm Outlier The PMOS-input folded cascode at 180 nm required 16 simulations to converge — nearly twice the next-longest case (FC-N at 40 nm, 9 simulations). The FC-P trajectory in Fig. 5 illustrates this outlier. The near-miss trajectory reveals an extremely narrow feasible region: • R4: A v = 59.3 (short by 0.7 dB), PM = 46.9° (short by 13.1°) — GBW passes at 115.3 but gain and PM fail. Pushing GBW higher cost gain and PM. • R10: A v = 60.5 dB passes, GBW = 99.9 MHz (short by 0.1 MHz), PM = 58.7° (short by 1.3°) — three metrics within 2% of target but two fail. • R13: A v = 59.9 dB (short by 0.1 dB), all other metrics pass — fails by 0.1 dB on gain. The subsequent R14 similarly fails only PM by 0.3°. • R15: A v = 60.2, GBW = 102.3, PM = 60.1°, SR+ = 100.1, SR− = 82.5 — all pass with narrow margins. This trajectory illustrates how a narrow feasible region increases the number of rounds required for convergence. SR specifications are met throughout; the difficulty lies in the tight coupling among A v , GBW, and PM. The LLM's design equations are structurally correct, but in this single-stage topology, shared devices and parasitic effects create an extremely tight design space where improving one of these metrics worsens another. Within the first 8 rounds, A v and PM were within 1–2 units of their targets (Av ≈ 58–59 dB, PM ≈ 59°), and GBW had stabilized near 105–111 MHz, indicating the framework reached the feasible region quickly. The remaining 8 rounds (R8–R15) navigated this narrow tradeoff window; the margins at convergence (0.2 dB, 0.1°, 2.3 MHz) confirm the topology operates near its feasibility boundary. The per-round pass/fail pattern (R13 fails only A v by 0.1 dB; R14 fails only PM by 0.3°) illustrates this tight coupling rather than systematic failure in any single metric. Notably, FC-P converges in 8 simulations at 40 nm — still the longest among 40 nm topologies, but far fewer than the 16 required at 180 nm. The difference reflects the interaction between specification targets and topology constraints: the higher gain target at 180 nm (60 dB vs. 40 dB) pushes the folded cascode closer to its feasibility boundary, narrowing the design space further. This confirms that convergence difficulty is driven by how tightly the specifications constrain a given topology, not by the process node itself. More broadly, convergence difficulty across all families is topology-dependent rather than polarity-dependent: the folded cascode is the most difficult family at both nodes, while the Miller-compensated PMOS variants converge faster than their NMOS counterparts at both nodes (3 vs. 6 at 180 nm, 3 vs. 8 at 40 nm). E. Structural Correctness: Representative Analysis Structural correctness — the requirement that the LLM correctly identifies which devices govern each specification and the direction of their influence — is central to the convergence claim. While 100% convergence across 12 topology–node combinations provides indirect evidence of structural soundness, this section provides direct verification by examining LLM-generated equations from a representative excerpt of the 2SMC-N topology at 40 nm. Table IV shows the LLM's equation for each specification alongside the governing devices it identifies, and the correctness assessment based on standard analog circuit theory. The LLM correctly identified: (a) the two-stage gain decomposition with the appropriate g m and r o terms for each stage; (b) that GBW is set by the first-stage g m1 and compensation capacitor, not by the second stage; (c) that SR+ is limited by the tail current charging C c (internal slewing), while SR− is limited by the output-stage current discharging C L (external slewing) — a distinction specific to Miller- compensated topologies; (d) that the non-dominant pole depends on g m8 /C L , making M8 the governing device for phase margin; and (e) the RHP zero cancellation strategy using the nulling resistor. These device-to-specification mappings are consistent with standard two-stage OTA design theory and ensure that the prediction-error feedback steers sizing adjustments in the correct direction. The folded cascode and current-mirror topologies require the LLM to additionally identify cascode bias voltage generation, folded current steering paths, and multi-branch mirror networks across 18 transistors. Complete convergence across all eight FC and CM topology–node combinations supports the generality of this structural soundness across all three OTA families. VI. DISCUSSION A. Why the Framework Works The framework succeeds by decomposing analog sizing into three complementary tasks, each handled by the component best suited to it. First, the LLM provides structural circuit understanding: it derives fresh, topology-specific equations from each netlist, providing a causal model of the circuit that anchors its sizing adjustments across rounds — ensuring convergent rather than oscillatory behavior. This causal anchoring is what distinguishes the framework from LLM-as- optimizer approaches, where the LLM proposes adjustments without an explicit model of how specifications relate to device dimensions. This is what enables the framework to 10 generalize across topologies without per-circuit modification: the equations emerge from the LLM's structural analysis of each individual netlist. Second, the calibration loop provides parametric accuracy that the LLM cannot achieve from first principles. Third, the prediction-error feedback provides robustness against analytical model errors that persist after calibration. Together, these three components explain why convergence speed correlates with topology-specific feasibility margins (Section V-D) rather than with prediction accuracy (Section V-B) — the measurement infrastructure, not the equation quality, determines the convergence trajectory. B. Architectural Robustness and Structural Correctness While the deterministic calibration scripts bound the impact of parametric errors — measured values override analytical estimates at every round — the framework does require that the LLM's equations be structurally correct. A structurally incorrect equation (e.g., predicting that gain increases when it actually decreases with a parameter change) would drive the design away from the target rather than toward it. Section V-E provides empirical verification of this property. This requirement distinguishes the proposed approach from black- box methods: the LLM must understand which devices govern each specification, not merely search a parameter space. The fresh-session design (no conversation history across rounds) is a deliberate methodological choice representing a worst-case operating mode. The LLM receives each round's prompt without memory of prior rounds, so convergence depends entirely on the information provided by calibrate.py, not on the LLM's reasoning continuity or incremental tuning. This demonstrates that convergence is a property of the framework architecture; a conversational mode with cumulative history could potentially reduce round counts but is not required. C. Qualitative Comparison Direct numerical comparison of simulation counts across methods is methodologically problematic because different works use different circuits, specifications, process nodes, and success criteria. For example, LEDRO [7] tests 22 topologies but uses a Figure of Merit (FoM) optimization target rather than hard specification thresholds; EEsizer [6] targets multiple performance metrics across several technology nodes; AutoSizer [12] tests 24 circuits of varying complexity with different difficulty tiers. A more informative comparison examines the qualitative properties of each approach. The BO initialization study by James et al. [2], recently published in IEEE TCAS-AI, provides a particularly relevant point of comparison: it tests two-stage Miller-compensated, folded cascode, and telescopic cascode OTA topologies at 45 nm CMOS — two of which (two-stage Miller, folded cascode) are among the families validated in this work — with various initialization strategies. Their specification targets (Gain ≥ 45 dB, GBW ≥ 20 MHz, PM ≥ 45°, Power ≤ 200 μW) are representative of moderate- performance applications, while the present work targets more aggressive specifications (Gain ≥ 40–60 dB, GBW ≥ 100–200 MHz, PM ≥ 60°, SR ≥ 50–100 V/μs). While BO-based methods and the proposed framework address the same design problem (sizing OTA-class amplifiers to meet specification targets), they differ fundamentally in what they produce and how they can be used in a design flow: 1) Output type. BO and existing LLM-based methods produce final device dimensions — a point in the design space — in some cases with reasoning traces [10], [11] but without executable equations. The proposed framework produces a calibrated sizing function constituting an auditable record of the sizing rationale. 2) Interpretability and design review. As detailed in Section I, the framework's output enables traceability and diagnostic transparency absent from black-box approaches. 3) Initialization and pre-characterization. BO requires initial sample generation — James et al. investigate initialization strategies for selecting 16 initial points and report design closure in 21–28 total simulations (16 initial + 5–12 BO iterations) depending on topology and initialization strategy. The proposed framework requires no initial samples, no training data, and no pre-characterization — the LLM derives equations from the netlist alone, and the calibration loop self- calibrates from a single DC OP simulation. Convergence is TABLE IV STRUCTURAL CORRECTNESS VERIFICATION – LLM-DERIVED EQUATIONS FOR 2SMC-N (40 NM) Specification LLM-Derived Equation Governing Devices Direction Correct? DC Gain A v = g m1 (r o2 ‖ r o4 ) · g m8 (r o8 ‖ r o7 ) M1/M2 (1st-stage g m ) M3/M4 (1st-stage load) M8 (2nd-stage g m ) M7 (2nd-stage load) ✓ Increasing g m1 or g m8 , or increasing r o of load devices, increases gain GBW GBW = g m1 / (2π·C c ) M1 (input transconductance) C c (compensation) ✓ Increasing g m1 or decreasing C c increases GBW SR+ SR pos = I tail / C c M5 (tail current source), C c ✓ Increasing tail current or decreasing C c increases positive SR SR− SR neg = I 7 / C L M7 (output-stage current sink), C L ✓ Increasing M7 current increases negative SR PM PM ≈ 90° − tan -1 (ω ugb / p 2 ), p 2 = g m8 /C L M8 (non-dominant pole via g m8 ), C L ✓ Increasing g m8 pushes p 2 higher, improving PM RHP Zero z = g m8 / C c , cancelled by R = 1/g m8 M8 (zero location) R = R z (nulling resistor) ✓ Setting R = 1/g m8 moves zero to infinity 11 achieved in 2–16 total simulations (median 6.5) with no initialization phase. 4) Cross-node portability. The proposed framework self- calibrates across nodes without modification, as the one-shot DC OP extraction automatically captures process-dependent parameters that vary between nodes. James et al. validate at a single node (45 nm); their BO workflow is trained on simulation data from that node, so the paper does not demonstrate cross-node portability; moving to a new node would likely require new simulations and re-running the BO workflow, including retraining the surrogate. Among LLM-based approaches, the differentiation is similar: as detailed in Table I, existing methods span a range of LLM roles — from direct optimization [6] to multi-agent collaboration [10], [11] — but none produce calibrated analytical design equations in executable form, and none provide quantitative analysis demonstrating that convergence is decoupled from prediction accuracy. VII. CONCLUSION We have demonstrated a self-calibrating framework for analog circuit sizing that combines LLM-derived design equations with one-shot DC OP calibration and prediction- error feedback. The framework achieves all target specifications across 12 topology–node combinations spanning three OTA families at two CMOS process nodes. Convergence despite large initial prediction errors confirms that convergence is a property of the measurement-feedback architecture, not of equation accuracy. The calibrated equations provide interpretable, auditable sizing rationale — a property absent from both black-box optimization and existing LLM-based methods. More broadly, the demonstrated ability of a frontier LLM to derive structurally correct, topology- specific design equations from raw netlists — without training, fine-tuning, or per-topology prompt customization — suggests that LLMs can serve as automated design-equation generators for analog circuits, complementing rather than replacing the optimization-based and knowledge-based methods that dominate the current landscape. R EFERENCES [1] W. Lyu, F. Yang, C. Yan, D. Zhou, and X. Zeng, "Batch Bayesian optimization via multi-objective acquisition ensemble for automated analog circuit design," in Proc. Int. Conf. Mach. Learn. (ICML), 2018, p. 3306–3314. [2] A. James, Z. H. Kong, S. K. Ata, K. M. M. Aung, K. S. Yeo, C. S. Foo, and A. James, "The initialization effect: Refining Bayesian optimization for circuit design," IEEE Trans. Circuits Syst. Artif. Intell., vol. 3, no. 1, p. 38–47, 2026. [3] M. del Mar Hershenson, S. P. Boyd, and T. H. Lee, "Optimal design of a CMOS op-amp via geometric programming," IEEE Trans. Comput.- Aided Design Integr. Circuits Syst., vol. 20, no. 1, p. 1–21, Jan. 2001. [4] K. Settaluri, A. Haj-Ali, Q. Huang, K. Hakhamaneshi, and B. Nikolić, "AutoCkt: Deep reinforcement learning of analog circuit designs," in Proc. Design, Autom. Test Eur. Conf. (DATE), 2020, p. 490–495. [5] P. G. A. Jespers and B. Murmann, Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables. Cambridge, U.K.: Cambridge Univ. Press, 2017. [6] C. Liu and D. Chitnis, "EEsizer: LLM-based AI agent for sizing of analog and mixed signal circuit," IEEE Trans. Circuits Syst. I, Reg. Papers, 2026, doi: 10.1109/TCSI.2025.3646359. [7] D. V. Kochar, H. Wang, A. P. Chandrakasan, and X. Zhang, "LEDRO: LLM-enhanced design space reduction and optimization for analog circuits," in Proc. IEEE Int. Conf. LLM-Aided Design (ICLAD), 2025, p. 141–148. [8] N. S. K. Somayaji and P. Li, "LLM-USO: Large language model-based universal sizing optimizer," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 45, no. 4, p. 1907–1920, Apr. 2026, doi: 10.1109/TCAD.2025.3604643. [9] Y. Yin, Y. Wang, B. Xu, and P. Li, "ADO-LLM: Analog design Bayesian optimization with in-context learning of large language models," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design (ICCAD), 2024, p. 1–9. [10] M. Ahmadzadeh, K. Chen, and G. Gielen, "(Invited Paper) AnaFlow: Agentic LLM-based workflow for reasoning-driven explainable and sample-efficient analog circuit sizing," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design (ICCAD), 2025, doi: 10.1109/ICCAD66269.2025.11240818. [11] J. Shen, Z. Chen, J. Zhuang, J. Huang, F. Yang, L. Shang, Z. Bi, C. Yan, D. Zhou, and X. Zeng, "Atelier: An automated analog circuit design framework via multiple large language model-based agents," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 45, no. 1, p. 31–44, 2026. [12] X. Yu, D. Torbunov, S. Mandal, and Y. Ren, "AutoSizer: Automatic sizing of analog and mixed-signal circuits via large language model (LLM) agents," arXiv preprint arXiv:2602.02849, 2026. [13] Z. Wei, Z. Kong, Y. Wang, D. Z. Pan, and X. Tang, "TopoSizing: An LLM-aided framework of topology-based understanding and sizing for AMS circuits," arXiv preprint arXiv:2509.14169, 2025. [14] X. Wu et al., "EasySize: Elastic analog circuit sizing via LLM-guided heuristic search," arXiv preprint arXiv:2508.05113, 2025. [15] S. Xu, H. Zhi, J. Li, and W. Shan, "LLMACD: An LLM-based analog circuit designer driven by behavior parameters," in Proc. Int. Symp. Electron. Design Autom. (ISEDA), 2025, p. 157–162. [16] C. Liu, W. Chen, A. Peng, Y. Du, L. Du, and J. Yang, "AmpAgent: An LLM-based multi-agent system for multi-stage amplifier schematic design from literature for process and performance porting," arXiv preprint arXiv:2409.14739, 2024. Antonio J. Bujana (Graduate Student Member, IEEE) received the B.S. degrees in engineering (electrical and biomedical) and the M.S. degree in engineering (electrical) from LeTourneau University, Longview, TX, USA, in 2015 and 2016, respectively. He is currently pursuing the Ph.D. degree in electrical engineering at Texas A&M University, College Station, TX, USA. He has over 10 years of industry experience with Collins Aerospace. He is currently an Assistant Professor of electrical engineering at Benedictine College, Atchison, KS, USA. His research interests include using large language models (LLMs) for circuit design automation. Aydin I. Karsilayan (Member, IEEE) received the B.S. and M.S. degrees in electrical engineering from Bilkent University, Ankara, Turkey, in 1993 and 1995, respectively, and the Ph.D. degree from Portland State University, Portland, OR, USA, in 2000. He joined Texas A&M University, College Station, TX, USA, in 2000, where he is currently an Associate Professor in electrical and computer engineering. His current research interests include high-frequency analog filters, data converters, automatic tuning, mixed-mode integrated circuit design, RF communication circuits, and power harvesting. He has served as an Organizing Committee Member for the IEEE MWSCAS 2014. He has served as an Associate Editor for the IEEE T RANSACTIONS ON CIRCUITS AND SYSTEMS—I: Regular Papers, from 2002 to 2004, and the IEEE Transactions on Circuits and Systems—I: Express Briefs, from 2006 to 2010.