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Ternary Memristive Logic: Hardware for Reasoning Realized via Domain Algebra
Chao Li
Intelligence
Status: succeeded | Model: Gemma-4-26B-A4B | Prompt: intel-v1 | Confidence: 94%
Last extracted: 4/26/2026, 4:35:33 PM
Summary
This paper proposes a novel hardware architecture for ternary memristive logic that implements the 'Domain-Contextualized Calculus' (CDC) framework. Unlike traditional neural network crossbars that store numerical weights, this system uses 1T1R memristive junctions to store complete, domain-scoped logical assertions (holds, negated, or undefined). The core contribution is a structure-preserving mapping (homomorphism) between a materialized domain algebra and a physical crossbar topology, where domains are represented by isolated arrays, specialization is represented by directed wiring, and relation typing is controlled by meta-array driven gates. The system was validated using an ICD-11 respiratory disease classification implementation, demonstrating that reasoning can be performed through direct voltage application and current reading without a symbolic processing layer.
Entities (6)
Relation Signals (4)
1T1R Cell → isusedin → Memristive Crossbar
confidence 100% · This paper assumes a 1T1R architecture throughout (Section 4.3).
Domain Algebra → mapsto → Memristive Crossbar
confidence 100% · We establish a structure-preserving mapping from a domain algebra to crossbar topology.
Memristive Crossbar → implements → CDC Framework
confidence 95% · The physical layout thus embodies the algebra; changing wiring changes reasoning semantics.
ICD-11 → isimplementedon → Memristive Crossbar
confidence 90% · We detail an ICD-11 respiratory disease classification chip...
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Abstract
Abstract:Memristive crossbars store numerical weights needing aggregation and decoding; a single junction means nothing alone. This paper presents a fundamentally different use: each junction stores a complete, domain-scoped logical assertion (holds/negated/undefined). Ternary resistance states encode these values directly. We establish a structure-preserving mapping from a domain algebra to crossbar topology: domains become isolated arrays, specialization becomes directed wiring, relation typing controls inheritance gates, and cross-domain links become explicit registers. The physical layout thus embodies the algebra; changing wiring changes reasoning semantics. We detail an ICD-11 respiratory disease classification chip (1,247 entities, ~136k 1T1R junctions) enabling domain scoping, three-valued logic, transitive cascade, typed inheritance, and cross-axis queries. Behavioral simulation (sigma_log=0.15, SNR=20dB) shows error-free operation across 100,000 trials per task with wide tolerance margins. Where prior work unified representation and computation in software, this work unifies them in hardware: reading one junction answers one question, without symbolic interpretation.
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- Source: https://arxiv.org/abs/2604.20891v1
- Canonical: https://arxiv.org/abs/2604.20891v1
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Ternary Memristive Logic: Hardware for Reasoning Realized via Domain Algebra Chao Li Deepleap.ai lichao@deepleap.ai Abstract Memristive crossbar arrays are widely used to perform matrix–vector multiplication in memory, but each junction stores only a numerical weight—a fragment whose meaning emerges only after aggregation, activation, and external decoding. A single junction, by itself, answers nothing. This paper explores a fundamentally different use of the same hardware. Building on the CDC framework (Li, Wang & Zhao, 2026a–c), we design a system in which each memristive junction stores a complete, domain-scoped logical assertion: whether a specific relation between two concepts holds, is negated, or is undefined within a given domain. Reading one junction directly answers one question, without aggregation or interpretation. The key contribution is not the use of ternary states, but a structure-preserving mapping from a materialized CDC domain algebra to a memristive crossbar topology. Under this mapping, domains become physically isolated arrays, specialization becomes directed inter-array wiring, relation typing controls inheritance through gated connections, and cross-domain links are realized as explicit bridge registers. In this design, the physical organization of the chip encodes the algebra itself: modifying the wiring changes the reasoning semantics. We present a concrete implementation for ICD-11 respiratory disease classification (1,247 entities, ~136,000 junctions) using 1T1R cells. The system supports domain scoping, three-valued logic, transitive classification, typed inheritance, and cross-axis reasoning through a combination of intra-array cascades and cross-reference registers. Behavioral simulation under realistic device variability (σlog=0.15 _ =0.15, SNR = 20 dB) shows error-free operation across 100,000 trials per task, with substantial tolerance margins. Prior work established that CDC unifies representation and computation in software. This paper demonstrates the same unification in hardware: when each stored element carries complete semantics, reasoning reduces to applying voltages and reading currents—no symbolic processing layer required. 1. Two Kinds of "In-Memory Computing" 1.1. The Neural Network Kind: Junctions as Fragments A memristive neural network accelerator stores a weight matrix W in a crossbar array. Each junction (i, j) holds a conductance value GijG_ij representing weight wijw_ij. When a voltage vector V is applied to the input wires, the output current at wire j is: Ij=∑iViGijI_j= _iV_i\,G_ij This is matrix-vector multiplication — performed in memory, with no data movement. This is genuinely valuable: it eliminates the von Neumann bottleneck for this specific operation. But what does junction (3, 7) mean? It means: "the weight connecting input neuron 3 to output neuron 7 in layer k is 0.73." This is a fragment. By itself, it answers no question. To produce a meaningful answer — "this image is a cat" — the system must: 1. Aggregate the entire row’s outputs (sum of currents) 2. Apply a nonlinear activation function (external circuit) 3. Route the result to the next layer (interconnect) 4. Repeat for every layer 5. Apply softmax and threshold (external logic) 6. Decode the output class (lookup table) Steps 2–6 happen outside the crossbar. The crossbar computes dot products; everything else is external. The junction stores a number. The number means nothing alone. 1.2. The CDC Kind: Junctions as Complete Assertions Now consider a different use of the same hardware. Junction (3, 7) in a specific crossbar array means: "In the anatomical classification world, Streptococcal Pneumonia (row 3) IS_A Pneumonia (column 7)." And its resistance state means: Resistance State Meaning Low (conducts) +1 Yes, this classification holds High (blocks) –1 No, this classification is explicitly negated Intermediate 0 This classification is not defined in this domain What does reading this one junction tell you? It tells you: in the anatomical domain, Streptococcal Pneumonia is classified as a type of Pneumonia. That is a complete clinical answer. Not a fragment. Not a partial dot product. A full, auditable, domain-scoped medical classification. No aggregation needed. No activation function. No decoder. One junction, one read, one answer. 1.3. Why This Difference Matters The difference is not about ternary vs. binary, or analog vs. digital. The difference is whether a single junction carries complete semantics. Neural Network Junction CDC Junction What it stores A numerical weight (0.73) A logical assertion (+1 / –1 / 0) What it means alone Nothing (fragment of a computation) A complete domain-scoped fact What reading it tells you One term of a dot product Whether a specific relation holds in a specific domain What else is needed for an answer Entire network + external circuits Nothing (or: cascade for multi-hop) Semantic coordinates Layer number, input index, output index (computational position) Domain, concept, relation, target concept (semantic position) In a neural crossbar, the position (i, j) tells you where in the computation this weight sits. In a CDC crossbar, the position tells you what clinical fact this junction represents. The position is the semantics. 1.4. The Central Claim When each junction in a memristive array carries complete CDC semantics — domain, relation, concepts, truth value — executing the reasoning reduces to applying voltages and reading currents, with no symbolic interpretation step in between. The rest of this paper makes this precise: we establish the homomorphism between a materialized CDC domain algebra and a crossbar topology, specify the 1T1R cell and cascade circuit that realize it, introduce cross-reference registers for inter-axis bridges, and validate five reasoning capabilities by behavioral simulation. 1.5. Position in the CDC Series This paper is part of a program of work on domain-contextualized reasoning. The prior papers establish the framework at progressively more operational levels: • Paper 1 (Li, Wang & Zhao, 2026a): establishes @D as a modal necessity operator with Kripke-style possible-world semantics. The representational claim: domain belongs in predicate arity, not metadata. • Paper 2 (Li, Wang & Zhao, 2026b): establishes the computable domain algebra — a Heyting algebra (their Theorem 4.9) with a typed Galois connection governing inheritance (their Theorem 4.19), and rank-1 neural convergence conditions (their Theorem 8.4). • Paper 3 (Li & Wang, 2026c): establishes representation-computation unity (RCU) — writing a CDC record defines its inferential behavior; reasoning is CRUD on stored four-tuples. A working Python+Prolog engine demonstrates the claim. This paper establishes that the same representation-computation unity dissolves the storage-computation boundary in physics as well as in software. The domain algebra of Paper 2 — materialized at compile time into a specific lattice — maps onto a memristive crossbar topology; the CRUD operations of Paper 3 map onto voltage writes and current reads. The paper claims no new algebra. Every algebraic result invoked below is from Paper 2. The contribution is the physical mapping and the circuit design that realizes it. 2. Background 2.1. Memristive Crossbar Arrays A crossbar array is a grid of horizontal word lines and vertical bit lines, with a memristive device (variable resistor) at each intersection. Three operations: • Write: Program each device to a target resistance state by applying voltage pulses. • Read: Apply a voltage to a word line; measure current at each bit line. Current through junction (i,j) = ViV_i / RijR_ij = ViV_i ⋅· GijG_ij. • Compute (in neural mode): Apply a voltage vector to all word lines simultaneously; output current vector = conductance matrix × voltage vector. Passive crossbars with two-terminal memristors suffer from sneak-path currents: a voltage applied to row i and sensed on column j drives not only the target junction (i,j) but also parasitic paths through unselected junctions. For arrays beyond ~100 junctions, this is the dominant source of read error and the reason commercial crossbar products universally adopt 1T1R cells — a selector transistor in series with each memristor, which eliminates sneak paths by electrically isolating unselected rows (Yu et al., 2011; Chen et al., 2015). This paper assumes a 1T1R architecture throughout (Section 4.3). 2.2. The Precision Problem Neural crossbars require 4–8 bit precision per junction (16–256 resistance levels) to faithfully represent continuous weight values. Achieving and maintaining this precision across millions of devices is the primary obstacle to commercialization: • Device-to-device variability • State drift over time • Read noise between adjacent levels • Programming endurance degradation 2.3. The CDC Framework (Summary) Paper 1 defines a CDC four-tuple as ⟨c,r,c′,d⟩ c,r,c ,d where c, c’ are concepts, r is a relation predicate, and d is a domain specification. An assertion r(c, c’, d) takes a value in +1, 0, –1: • +1: r(c, c’) holds in world wdw_d • –1: r(c, c’) is explicitly negated in wdw_d • 0: r(c, c’) is not defined in wdw_d (semantically irrelevant) The third state is not "unknown" — it means the question has no answer in this domain. "Is Aspirin a drug?" is undefined in @Music. Not unknown. Meaningless. Paper 2 establishes the domain algebra DA = (D, ⊑ , ⊓ , ⊔ , →, ⊥ , ⊤ , τ, F) where: • ⊑ is the specialization order on domain strings (a partial order) • ⊓ is meet; ⊔ is join • → is Heyting implication • τ: R → monotone, non-monotone is the relation typing function stored in a meta-fiber • F(d) is the fiber: the set of assertions scoped to d Paper 2 further establishes that DA is a Heyting algebra (their Theorem 4.9); that reindexing from a parent fiber to a child fiber is a τ-typed Galois connection (α, γτ _τ), with γτ _τ undefined for non-monotone relations (their Theorem 4.19); and that monotonicity is equivalent to γτ∘α _τ α being a closure operator (their Corollary 4.20). Paper 3 further provides cross-fiber bridge predicates (same_entity_across, analogous_to, fuses_with) that link concepts across fibers that are not in a ⊑ relation. 2.4. Related Hardware Approaches Several hardware paradigms store or compute logical/semantic information in memristive arrays. This paper’s contribution is distinct from each. Hyperdimensional Computing (HDC) / Vector Symbolic Architectures. Kanerva (2009) and subsequent in-memory implementations (Karunaratne et al., 2020; Wu et al., 2021) encode symbols as high-dimensional bipolar vectors and perform symbolic operations through element-wise operations in memristive arrays. HDC junctions store vector components — a single junction is one dimension of a distributed representation, and meaning requires reading the entire vector. A CDC junction stores a complete assertion — meaning is localized to a single device. HDC trades localizability for noise robustness; CDC prioritizes localizability for auditability and domain scoping. Stateful Memristive Logic. Borghetti et al. (2010), Kvatinsky et al. (2014), and Talati et al. (2016) use memristors as logic gates: applying voltage sequences causes resistance states to compute material-level IMPLY, NAND, or related primitives. These approaches embed Boolean logic in physics. CDC embeds three-valued intuitionistic logic with domain scoping, which stateful logic cannot natively express. Analog Content-Addressable Memory. Li et al. (2020) use memristors to build analog ternary CAMs for similarity search. A TCAM performs pattern matching across a flat store; entries can be rearranged without changing semantics. In CDC, the physical layout is the algebra — the directed wiring topology encodes the specialization order, and rearranging the wiring changes the inference. This is the central structural difference argued in Section 3. Neuromorphic Chips. IBM TrueNorth (Merolla et al., 2014), Intel Loihi 2, and BrainScaleS implement spiking neural networks. Reasoning emerges from population dynamics over many neurons. CDC reasoning is localized to individual junctions. Knowledge Graph Accelerators. Recent ISCA/MICRO work builds specialized hardware for embedding-based KG completion. These accelerate matrix operations on pre-trained embeddings; they do not store symbolic assertions directly. In this design space, CDC occupies a previously unfilled position: localized, symbolic, three-valued, domain-scoped, auditable. 3. From Algebra to Physics: The Structural Homomorphism We now present the mapping Φ formally. Readers unfamiliar with the CDC algebra may interpret it operationally as a compile-time embedding of domain structure into crossbar topology: domains become arrays, inheritance becomes wiring, and relation typing controls current flow. The formal statements below make this correspondence precise. The central contribution of this paper is that the Heyting algebra of Paper 2, once materialized at compile time into a specific domain lattice, maps structure-preservingly onto a memristive crossbar topology. We stress that Paper 2 has already done the algebraic work — the results we need are already proved there. This section defines the materialized algebra DA∗DA^*, the crossbar topology CTCT, the map Φ:DA∗→CT ^* , and shows that Φ preserves each algebraic property. 3.1. Compile-Time Materialization The domain algebra DA defined in Paper 2 is a general algebraic framework; any specific application instantiates it with a concrete set of domains, a concrete specialization order, a concrete set of bridges, and a concrete typing function. We call this instantiation a materialized domain algebra, denoted DA∗DA^*. The hardware presented here realizes a single materialized snapshot of DA∗DA^*. At compile time, the domain lattice is crystallized into directed wiring between arrays; the typing function is crystallized into the state of a meta-array; cross-fiber bridges are crystallized into cross-reference registers. Once the chip is fabricated, this structure is fixed: the memristive states within each array remain programmable (supporting INSERT, UPDATE, DELETE of individual assertions), but the inter-array topology does not. Runtime evolution of the domain lattice itself — for example, through mechanisms that split a domain when a new assertion creates a contradiction — is handled in software and falls outside the scope of this physical implementation. Such mechanisms produce a new DA∗DA^*, which can be compiled to a new chip or loaded onto a reconfigurable platform; neither extension is pursued here. This framing has two consequences for what follows. First, we do not need to commit to whether the specialization order in DA∗DA^* is a tree, a DAG with multiple inheritance, or some other partial order shape: whatever partial order the compiler hands us, we materialize it as directed wiring. Second, concepts that participate in multiple classification axes simultaneously — for example, a disease that belongs to an anatomical classification, an etiological classification, and a clinical classification at the same time — are handled not by making one domain the child of multiple parents, but by treating each classification axis as its own domain tree and linking concepts across axes through bridges. This is exactly how Paper 3 §9 represents ICD-11 multi-axis classification: via same_entity_across bridges, not via multi-parent ⊑ edges. 3.2. The Physical Structure: Crossbar Topology Define the physical structure of a memristive crossbar system as: CT=(A,⊑A,W,G,S,M,B)CT=(A, _A,W,G,S,M,B) Symbol Meaning Physical realization A Set of crossbar arrays Physically separate array regions on chip ⊑A _A Connection ordering between arrays Directed wiring: array a1 can send current to a2 W Set of junctions across all arrays 1T1R cells at crossbar intersections G Gate states on inter-array connections Transistor switches between arrays: ON/OFF S: W → +1, 0, –1 State function: each junction’s resistance RlowR_low / RmidR_mid / RhighR_high M Meta-array storing τ Small crossbar whose junction states drive G B Cross-reference register bank Registers linking concepts across non-comparable domains 3.3. The Mapping Φ:DA∗→CT ^* Φ is a family of six sub-mappings that jointly act on the carriers and operations of DA∗DA^*. Informally, Φ takes every algebraic component of DA∗DA^* and returns its physical counterpart in CTCT; formally, it is the ordered collection (ΦD,ΦF,ΦS,Φ⊑,Φτ,ΦB)( _D, _F, _S, _ , _τ, _B): Domain Algebra (DA∗DA^*) Sub-mapping Crossbar Topology (CTCT) Domain d ∈ D ΦD _D Array ada_d ∈ A Fiber F(d) ΦF _F Junction states in array ada_d Assertion state +1, 0, –1 ΦS _S RlowR_low / RmidR_mid / RhighR_high Specialization dcd_c ⊑ dpd_p Φ⊑ _ Directed wire from adpa_d_p to adca_d_c Typing τ, unfolded over inheritance edges Φτ _τ Meta-array states driving gate transistors G Bridge predicate bridge(c, c’, d1, d2) ΦB _B Entry in cross-reference register bank B Note on Φτ _τ. In Paper 3, τ is stored as a small number of four-tuples of the form from: r, rel: has_property, domain: @Meta@Logic, to: monotone/non_monotone — one entry per relation r, independent of any specific domain pair. Physically, however, each parent-child inheritance edge that involves relation r needs its own gate transistor, so Φτ _τ does not simply copy τ: it unfolds τ across the inheritance edge set. For each triple (r, dpd_p, dcd_c) where dcd_c ⊑ dpd_p, Φτ _τ produces a gate G(r, dpd_p, dcd_c) whose state is determined by τ(r). The meta-array M stores one ternary junction per relation type (the underlying τ), and a CMOS buffer tree amplifies and replicates each meta-junction’s state to all gate transistors associated with that relation. The buffer tree is necessary because a single memristive junction cannot directly drive thousands of transistor gates — its current output is orders of magnitude below the required fan-out. The tree is a standard logarithmic-depth driver fabric (typical fan-out of 4 per stage, ~6 stages to reach 8K gates), contributing negligible area and ~1 ns propagation delay to the gate-update path. For the ICD-11 chip of Section 4, this yields 8 meta-junctions driving ~8,600 gate transistors through ~60 buffer stages in total (distributed across relation types). Note on ΦB _B. Bridges in Paper 3 link concepts across fibers that are not in a ⊑ relation — for example, viral pneumonia’s identity across the anatomical and etiological classification axes. Because these links do not flow along the specialization order, they cannot be implemented by directed inter-array wiring; instead, we implement them as explicit cross-reference registers (Section 4.4). ΦB _B is therefore a separate mapping channel from Φ⊑ _ , and this separation is essential: collapsing bridges into ⊑ edges would corrupt the algebra. 3.4. Seven Lemmas: Φ Preserves the Domain Algebra We now state seven lemmas. Each is of the form "Paper 2 (or Paper 3, for bridges) establishes algebraic property X; Φ preserves X." Together they constitute Theorem 1. Lemma 3.4.1 (Fiber isolation). By Paper 2 Definition 3.3, F(d1) ∩ F(d2) = ∅ for d1 ≠ d2. Under Φ , arrays a_d1 and a_d2 are physically separate — non-overlapping regions with no shared word or bit lines. Proof: ΦD _D maps distinct domains to distinct arrays; ΦF _F maps disjoint fibers to junctions in disjoint arrays. Current applied to a_d1 cannot produce current in a_d2 without traversing either a gated inter-array connection (Φ⊑ _ ) or a cross-reference register access (ΦB _B). Both are explicit operations; neither is a leakage path. □ Lemma 3.4.2 (Ternary valuation). By Paper 2 Section 4.1, each assertion in F(d) takes a value in +1, 0, –1. Under ΦS _S, these map bijectively to RlowR_low, RmidR_mid, RhighR_high. Algebraic state Physical state Electrical behavior +1 (holds) RlowR_low (~10 kΩ ) High current — conducts 0 (undefined) RmidR_mid (~100 kΩ ) Intermediate current –1 (negated) RhighR_high (~1 MΩ ) Near-zero current — blocks Proof: A two-threshold comparator (IhighI_high > ImidI_mid > IlowI_low) distinguishes all three states. □ Why ternary, not binary: "Aspirin is contraindicated in pediatrics" (–1) requires active warning; "Aspirin has no established role in veterinary medicine" (0) requires no action. Binary encoding collapses both into "not true" and loses this safety-critical distinction. Lemma 3.4.3 (Specialization order). By Paper 2 Definition 4.2, ⊑ is a partial order on domain strings. Under Φ⊑ _ , for each pair (dc,dp)(d_c,d_p) in DA∗DA^* with dc⊑dpd_c d_p, there is a directed wire from adpa_d_p to adca_d_c. Incomparable domains are physically unconnected. Proof: the partial order of DA∗DA^* is given at compile time. Φ⊑ _ instantiates it as a directed inter-array graph: every covering pair in the Hasse diagram of (D, ⊑ ) becomes a physical wire; reachability in the array graph matches reachability in the order. The shape of the partial order — tree, DAG, or otherwise — is determined by DA∗DA^* and reproduced verbatim by Φ⊑ _ ; the physical mechanism is indifferent to this shape, as long as the fan-in at each array is within the driver’s capacity. □ Lemma 3.4.4 (Meet). By Paper 2 Definition 4.4, d1 ⊓ d2 is the longest common prefix (the greatest lower bound under ⊑ ). Under Φ , this corresponds to the greatest common ancestor in the directed array graph. Proof: By Lemma 3.4.3, the array graph mirrors (D, ⊑ ). The meet is the greatest lower bound of two elements in the partial order; under the physical graph, this is computable by intersecting the downward-closures of a_d1 and a_d2 and selecting the maximum — implementable as a short circuit trace. □ Lemma 3.4.5 (Heyting implication). By Paper 2 Theorem 4.9, d1 → d2 = ⊔ _Δ d | d ⊓ d1 ⊑ d2. Under Φ , this is the least upper bound of all arrays ada_d such that any path from ada_d passing through a_d1 also reaches a_d2. Proof: By Lemmas 3.4.3 and 3.4.4, ⊑ and ⊓ are preserved as reachability and common-ancestor operations on the array graph. The Heyting implication is the join of a downward-closed set; Paper 2 Lemma 4.7 (Prefix Distributivity) ensures this join is well-defined. Computationally, the implication is determined by a backward reachability trace: starting from a_d2, walk backward along ⊑A _A edges to find arrays whose every path through a_d1 terminates in a_d2. This is O(|A|) in the number of arrays. □ Lemma 3.4.6 (Typed Galois connection). By Paper 2 Theorem 4.19, (α, γτ _τ) is a Galois connection on the monotone subcategory of relations, with γτ _τ undefined on the non-monotone subcategory. Under Φτ _τ, for each inheritance edge (dcd_c ⊑ dpd_p) and each relation r, the gate G(r, dpd_p, dcd_c) is driven by the meta-junction encoding τ(r): • τ(r) = monotone → meta-junction at RlowR_low → gate driver output HIGH → G(r, dpd_p, dcd_c) ON → current can flow from adpa_d_p to adca_d_c for relation r. Physically: γτ _τ is defined on this edge for this relation; an inherited assertion exists in the child fiber. • τ(r) = non-monotone → meta-junction at RhighR_high → gate driver output LOW → G(r, dpd_p, dcd_c) OFF → no current path exists. Physically: γτ _τ is undefined on this edge for this relation; the assertion cannot be inherited. Proof: The gate does not filter inherited assertions — it enables or disables the electrical path. When G(r, dpd_p, dcd_c) is OFF, no current path exists for relation r on that edge. This is the physical realization of "undefined" in the typed Galois connection: not "checked and rejected," but "structurally impossible." Because Φτ _τ unfolds a single τ(r) value to all gates G(r, ⋅·, ⋅·) for that relation (Section 3.3), a single meta-junction state simultaneously governs all inheritance edges for r. □ Why this is the decisive distinction from TCAM: In a TCAM, all entries are equally accessible; preventing inheritance requires a software rule that can be bypassed, misconfigured, or forgotten. In CT, G(r, dpd_p, dcd_c) is a physical switch. When OFF, no software can make the current flow through it. The constraint is not in code — it is in physics. Lemma 3.4.7 (Closure property). By Paper 2 Corollary 4.20, γτ∘α _τ α is a closure operator on monotone relations: (γτ∘α _τ α) ∘ (γτ∘α _τ α) = γτ∘α _τ α. Under Φ , this is physical write-idempotence: after reindexing has populated adca_d_c with inherited junctions from adpa_d_p, re-running the inheritance cycle writes the same junction states. Proof: Re-inheritance attempts to write values identical to those already present. RRAM and PCM devices tolerate redundant writes to the same target state with negligible state change (Wong & Salahuddin, 2015); the circuit is naturally idempotent at the device level. □ Lemma 3.4.8 (Bridge preservation). By Paper 3 Section 9, bridge predicates such as same_entity_across, analogous_to, and fuses_with link concepts across fibers whose domains are not in a ⊑ relation. Under ΦB _B, each bridge predicate instance is stored as an entry in the cross-reference register bank B. Read access to a bridge entry returns the target concept and domain without traversing ⊑A _A wiring. Proof: ΦB _B maps bridge four-tuples in DA∗DA^* to register entries in B. A bridge from (c,d1)(c,d_1) to (c′,d2)(c ,d_2) with incomparable domains is stored as a register entry indexed by (c,d1)(c,d_1) and returning (c′,d2)(c ,d_2). Reading the register is a constant-time operation orthogonal to ⊑A _A wiring; the bridge does not flow along the specialization order and therefore does not interact with the Galois connection or the inheritance gates. □ 3.5. Theorem 1 Theorem 1 (Structural homomorphism). Φ:DA∗→CT ^* preserves the full algebraic structure of the materialized CDC domain algebra: fiber isolation, ternary valuation, specialization order, meet, Heyting implication, typed Galois connection, closure property, and bridges. Proof: By Lemmas 3.4.1 through 3.4.8. □ 3.6. Why This Is Not TCAM: A Summary Property TCAM CDC Crossbar Topology (CTCT) Physical layout Flat: all entries in one array Structured: arrays connected by directed wiring + bridges Layout carries meaning No: entries can be rearranged arbitrarily Yes: wiring topology = domain lattice Domain scoping Software filter on match fields Physical array isolation Specialization order Not represented in hardware Directed inter-array connections Meet (⊓ ) Not computable from hardware Circuit trace: most specific common ancestor Heyting implication (→) Not representable Backward reachability on array graph Typed inheritance Software rule (bypassable) Physical gate G(r, dpd_p, dcd_c) (not bypassable) Cross-fiber bridges Not representable Cross-reference register bank Closure property Not applicable Re-running inheritance = no change A TCAM stores values. CTCT stores an algebra. 3.7. Five Reasoning Functions as Consequences The lemmas yield five reasoning capabilities as direct consequences: Consequence 1: Domain scoping follows from Lemma 3.4.1 — current in one array cannot leak to another without an explicit gated or register-mediated path. Consequence 2: Three-valued logic follows from Lemma 3.4.2 — each junction’s physical state IS its logical state. Consequence 3: Transitive classification follows from Lemma 3.4.1 + 3.4.2 — within an isolated array, the cascade mechanism (Section 4.3) computes transitive closure by iterating row-input/column-output cycles. Consequence 4: Typed knowledge inheritance follows from Lemma 3.4.3 + 3.4.6 — specialization order as directed wiring, Galois connection as meta-gated paths G(r, dpd_p, dcd_c). Consequence 5: Intra-array write-time consistency checking follows from Lemma 3.4.1 + 3.4.2 — because all explicitly stored assertions in a domain coexist in the same physical array, checking for immediate contradictions before writing is a single READ cycle on the same array. The validator IS the knowledge base. Transitive consistency across inherited assertions in other domains requires a full cascade check and is handled at a higher layer of the write controller. Cross-axis queries, where two or more incomparable domains are consulted in the same inference, are handled by Consequence 4 within each domain tree followed by ΦB _B register lookups across trees (Section 4.4). 3.8. CRUD Operations as Voltage/Current Operations Paper 3 Corollary 4 established that database operations on CDC four-tuples are simultaneously inference operations. Under Φ , those database operations become voltage and current operations: Database (Paper 3) Inference (Paper 3) Hardware (this paper) INSERT c, r, d, c’ Assert domain-scoped fact SET pulse at junction (c, r, c’) in ada_d SELECT WHERE domain=d Query within a world Voltage on row c in ada_d, sense current on column c’ DELETE c, r, d, c’ Retract belief Partial-RESET to RmidR_mid at that junction JOIN on domain Transitive inference Cascade read within ada_d (Section 4.3) FOREIGN KEY to meta-fiber Enforce type constraint Meta-array state driving G(r, dpd_p, dcd_c) Bridge lookup Cross-fiber reference Cross-reference register read Paper 3 dissolved the storage-computation separation in software. The same dissolution holds in hardware under Φ . 4. Putting It Together: The ICD-11 Reasoning Chip 4.1. What We Are Building A chip that performs domain-scoped medical classification for ICD-11 respiratory diseases. Given a disease entity and a classification axis, the chip returns the complete classification chain in hardware. Following Paper 3 §9, we treat ICD-11’s three classification axes — Anatomical, Etiological, Clinical — as three parallel domain trees rather than as multiple inheritance within one tree. Entities that belong in all three (e.g., Viral Pneumonia) are linked across trees by same_entity_across bridges. This matches the representational choice made in Paper 3 for the same data. 4.2. Physical Layout ICD-11 Reasoning ChipMaterialized domain treesControl and bridge logicShared sensing and cascade infrastructureRespiratoryArrayUpper⋯·saxis-local specializationInfectiousArrayViral⋯·saxis-local specializationAcuteArraySevere⋯·saxis-local specializationGATEGATEGATEMeta-Arrayτ storage + gate driversCross-Reference Register Bankcross-axis bridge lookupsRow drivers, column sense amplifiers, two-threshold comparators, cascade feedback path Figure 1: Publication-style layout of the ICD-11 reasoning chip. The top band shows three materialized domain trees as isolated crossbar families; arrows run consistently downward into the meta-array that governs typed inheritance; cross-axis queries are handled by a dedicated bridge-register bank; and the bottom band groups the shared sensing and cascade circuitry. 4.3. The Cascade Mechanism Consequence 3 (transitive classification) requires cascading reads within an array. We now specify the circuit that implements this process and analyze its complexity. Each domain array is organized as a square crossbar indexed by concept: the same concept appears as both a row (source) and a column (target). A single read cycle applies a voltage to one row and senses currents on all columns. For transitive closure, the column currents where output = +1 must be re-driven as row voltages in the next cycle. The cascade circuit implements the following sequence: Step Operation Cycle 1 Apply the row driver to concept CA40.00; column sense amplifiers read the resulting current vector. Thresholding Two-threshold comparators convert the analog readout into a ternary state vector T1∈+1,0,−1NT_1∈\+1,0,-1\^N. Latch state Store the positive frontier as S1=c′:T1[c′]=+1S_1=\c :T_1[c ]=+1\. Cycle k+1k+1 Pick the next unvisited concept c∈Skc∈ S_k, drive its row, sense all columns, and append new positive outputs to Sk+1S_k+1. Stop rule Terminate when a cycle yields no new +1+1 outputs, indicating that the root has been reached. Table 1: Cascade-read procedure used for transitive classification within a single domain array. Why only one row is activated per cycle. Activating two rows simultaneously would superpose their column-current signatures, and the two-threshold comparator could not distinguish "row A triggered this column at +1" from "row B triggered this column at +1, row C at –1, net +1." The circuit serializes the cascade frontier to preserve per-junction resolution. Why 0 and -1 states do not propagate. The intermediate current of the 0 state (RmidR_mid, ~2 μ ) and the near-zero current of the -1 state (RhighR_high, ~0.2 μ ) both fall below the positive-threshold comparator (IhighI_high = 6.32 μ ). They therefore cannot enter the latch and cannot be chosen as next-cycle row activations. Undefined and negated semantic paths are pruned from the cascade frontier purely by physical current thresholds, with no conditional-branching logic, no software filter, and no extra cycles. What takes a query optimizer a pass to compute in software is an inherent property of the circuit. This is a structural benefit of embedding three-valued logic in physics rather than layering it on top of binary computation. Why the total cycle count stays bounded. The apparent worst case "N concepts × 4 steps = 4N reads" does not occur because the cascade frontier does not fan out linearly: is_a is a tree, and a disease classifies into O(d) ancestors where d is the depth of the taxonomy (typically 4–6 for ICD-11). The actual cycle count is O(d), not O(N). Why threshold regeneration matters. The cascade is not continuous analog current flow — it is a sequence of discrete, digitized reads. Continuous analog propagation would accumulate read noise across cycles and collapse the three-state distinction after 2–3 hops. Each discrete read is threshold-restored to +1, 0, –1, preventing noise accumulation. This is the same principle as regenerative digital logic. Why 1T1R is required. In a passive crossbar, applying voltage to a row drives current through every junction on that row including junctions in RmidR_mid, producing a sneak-current background that can exceed the target signal for realistic array sizes. The 1T1R selector transistor ensures that only the explicitly addressed cell is active in a column, and only junctions in RlowR_low contribute to that column’s sensed current. Timing breakdown (nominal, per cascade cycle within one axis): Stage Time Notes Row driver rise (word-line charge) 1 ns Standard CMOS driver Word line + access-transistor settle 2 ns 1T1R access delay Column sense-amp integration 5 ns Dominant term; current mirror + capacitor integration Two-threshold comparator 1 ns Paired latched comparators Latch + control sequencer 1 ns Cascade-frontier update Per-cycle total ~10 ns Meta-array updates (τ writes) and bridge-register accesses run on separate paths and do not add to the cascade critical path. A τ update, when needed, incurs one meta-junction write plus a ~1 ns buffer-tree propagation delay (§3.3) before the new gate pattern is stable — orders of magnitude below the minutes-to-yearly timescale of knowledge-base updates. A 4-step classification cascade within one axis: ~40 ns. Full ICD-11 query across 3 axes plus cross-axis bridge lookups: ~120 ns. For comparison, the Paper 3 software engine on commodity hardware takes <20 ms for the same query — a ~5 order-of-magnitude reduction, driven not by clever optimization but by the absence of a software stack. 4.4. Cross-Reference Registers Bridges link concepts across axes. For ICD-11, the dominant bridge is same_entity_across — e.g., CA40.00 (Streptococcal Pneumonia) as the "same entity" in the Anatomical, Etiological, and Clinical axes. We implement the register bank as follows: • Indexed by (concept_id, axis_id): a 16-bit concept address plus a 2-bit axis tag • Returns a list of (concept_id, axis_id) pairs, one per axis where the same entity appears • Size for the respiratory chapter: ~3,000 entries (roughly one-third of concepts participate in cross-axis bridges), 8 bytes per entry, ~24 KB total — a negligible silicon footprint Bridge reads occur in parallel with axis cascade reads, adding no latency to the critical path. A full cross-axis query executes as: cascade within each axis, then read bridge registers to align the three result chains at the entity level. This register bank is the physical realization of ΦB _B (Lemma 3.4.8). It is deliberately kept structurally separate from the ⊑A _A wiring: bridges are not inheritance and must not be treated as such. 4.5. Specifications Parameter Value Note Classification axes 3 Anatomical, Etiological, Clinical Arrays per axis (avg) ~16 Taxonomic subdomains within each axis Total arrays 47 Across all three axes Junctions per array (avg) ~2,900 (61×48) Concepts × relations in that domain Cell structure 1T1R Selector transistor in series with memristor Total memristive junctions ~136,000 All domain arrays combined Meta-crossbar junctions 8 8 relation types in @Meta@Logic (τ only depends on r) Inter-array gate transistors ~8,600 τ unfolded across all inheritance edges Cross-reference register entries ~3,000 Bridges between axes Resistance states per junction 3 RlowR_low, RmidR_mid, RhighR_high Precision required 1.58 bits log2(3) — vs. 4–8 bits for neural Read circuit Two-threshold comparator vs. precision ADC for neural 4.6. Example: Full Diagnostic Query Clinical question: "Classify CA40.00 (Streptococcal Pneumonia) across all axes." Hardware operation: STEP 1: Select @Anatomical axis. Apply voltage at CA40.00 row of the leaf array. -> Cycle 1: +1 at "Pneumonia" column -> Cycle 2: Pneumonia -> +1 at "Lower_Resp_Infection" -> Cycle 3: Lower_Resp_Infection -> "Respiratory_Disease" -> Cycle 4: no new +1 outputs (STOP) RESULT: CA40.00 is a Respiratory Disease (anatomical axis), 4 cycles STEP 2: Read cross-reference register for (CA40.00, Anatomical). $→$ Returns: (CA40.00, Etiological), (CA40.00, Clinical) (The "same entity" appears in all three axes at these addresses.) STEP 3: Select @Etiological axis. Apply voltage at CA40.00 row. $→$ Cascade: Bacterial_Infection $→$ Infectious_Disease $→$ STOP RESULT: CA40.00 is an Infectious Disease (etiological axis), 3 cycles STEP 4: Select @Clinical axis. Apply voltage at CA40.00 row. $→$ Cascade: Acute_Lower_Respiratory $→$ STOP RESULT: CA40.00 is Acute Lower Respiratory (clinical axis), 2 cycles Total: 9 cascade cycles + 1 register read $≈$ 90 ns + 1 ns $≈$ 91 ns. Note that the bridge register in STEP 2 is read once and used to index into both subsequent axes — without bridges, STEP 3 and STEP 4 would need to re-derive CA40.00’s identity in the other axes from its classification, which is not in general possible. 5. Fabrication Feasibility and Behavioral Validation 5.1. Three-State Memristors: A Solved Problem Unlike neural accelerators that demand 4–8 bit precision (16–256 resistance levels), CDC reasoning requires only three states. Three-state memristive operation has been demonstrated in multiple material systems: • HfO2-based RRAM: SET (low R), RESET (high R), and partial-SET (intermediate R) are well-characterized states with resistance ratios >10× between adjacent levels. • Phase-change memory: Amorphous (high R), partial crystalline (mid R), and full crystalline (low R) provide three thermodynamically distinct states. The fabrication advantage is substantial: three widely-spaced levels tolerate much higher device variability than multi-level programming. The yield and reliability requirements are dramatically relaxed. 5.2. Scale 136,000 memristive junctions plus ~8,600 selector transistors and ~8,600 gate transistors for the respiratory chapter. The full ICD-11 (~85,000 entities, ~500 domains) would require approximately 7–10 million junctions — well within demonstrated crossbar capacities (Yao et al., 2020 demonstrated 2M+ junctions in a single wafer-scale design). 5.3. What Is Needed from a Fabrication Partner 1. A 1T1R memristive crossbar programmable to 3 stable resistance states (HfO2 RRAM or equivalent), with ≥ 10× resistance ratio between adjacent levels 2. CMOS-memristor BEOL integration at a conventional logic node (28 nm and below is standard for RRAM demonstrations) 3. Transistor-gated inter-array connections — access transistors driven by a CMOS buffer tree from the meta-array 4. Two-threshold current-mode sense amplifiers (paired latched comparators, substantially simpler than the ≥ 8-bit ADCs required for analog neural inference) 5. Row/column drivers and a cascade-feedback controller (standard digital CMOS) 6. A modest SRAM register bank for cross-axis bridges (~24 KB for the respiratory chapter) 7. Total 1T1R cell count: ~136,000 for the proof-of-concept respiratory chapter This is a modest fabrication target for any lab with operational 1T1R crossbar capability. 5.4. Behavioral Simulation To validate that all six reasoning capabilities function correctly under realistic device non-idealities, we implemented a Python + NumPy behavioral model of the full system. The code and raw output are released with the paper. Model parameters. • Three resistance states with 10× spacing: RlowR_low = 10 kΩ (+1), RmidR_mid = 100 kΩ (0), RhighR_high = 1 MΩ (–1) • Read voltage V_read = 0.2 V, giving nominal currents of 20, 2, and 0.2 μ respectively • Device variability: log-normal resistance distribution with σlog=0.15 _ =0.15 (15% on log scale, matching commercial HfO2 RRAM characterization) • Read noise: additive Gaussian on sense current, SNR = 20 dB (noise_std = signal / 10) • 1T1R selector: ideal switch; sneak paths eliminated by construction • Two-threshold comparator at geometric-mean thresholds: IhighI_high = 6.32 μ , IlowI_low = 0.632 μ Test suite at nominal operating point (100,000 trials per test). Test Query Expected Observed C1 (scope) Read within isolated array; check no column leakage to unrelated fiber Zero cross-array current 0 errors / 400,000 reads C2 (ternary) Per-state read fidelity for each of +1, 0, –1 Correct decode 0 errors / 300,000 reads C3 (cascade) 4-step classification CA40.00 → Pneumonia → Lower_Resp → Respiratory_Disease Correct chain 0 errors / 100,000 runs C4 (inheritance) Meta-gate decodes τ(r) under read noise ON for monotone, OFF for non-monotone 0 errors / 200,000 trials C5 (write check) Read-before-write detects same-pair contradiction Reject write 0 errors / 100,000 trials C6 (bridge) Cross-reference register lookup Deterministic 0 errors / 300,000 lookups All six tests pass at 100% under 100,000 trials. The empirical upper bound on the failure rate at the nominal operating point is therefore <10−510^-5; theoretical analysis (three states separated by ≥ 5σ margin at σlog=0.15 _ =0.15) predicts the true rate is ~10−1010^-10 or lower. Safety margin (variability sweep). To characterize the design envelope, we swept σlog _ from 0.10 to 0.50 holding SNR = 20 dB constant (simulation figure omitted). The per-state and cascade error rates are: σlog _ +1 error 0 error –1 error 4-step cascade 0.15 (nominal) <10−510^-5 <10−510^-5 <10−510^-5 <10−510^-5 0.20 <10−510^-5 <10−510^-5 <10−510^-5 <10−510^-5 0.25 0.001% 0.006% 0.001% 0.002% 0.30 0.011% 0.022% 0.014% 0.049% 0.35 0.080% 0.154% 0.072% 0.229% 0.40 0.270% 0.529% 0.226% 0.770% 0.50 1.244% 2.390% 1.163% 3.560% Three findings are worth noting. First, the design tolerates variability up to σlog≈0.25 _ ≈ 0.25 with no observable errors — a 67% headroom over the nominal value. Commercial HfO2 RRAM typically achieves σlog _ ≈ 0.10–0.20, placing the design comfortably inside the safe region. Second, the "0" (undefined) state is approximately twice as error-prone as ± 1 at any given variability. This is a structural property of any ternary encoding: the middle state is vulnerable to noise excursions in both directions, whereas the extreme states are vulnerable only in one. It is not a flaw of the design — it is a property of three-valued readout under Gaussian noise — but it justifies designing the undefined state to be the safe default: an assertion drifting from +1 or –1 toward 0 becomes "unanswerable," which a clinical controller can flag for refresh, rather than silently flipping to the opposite truth value. Third, cascade errors scale roughly as 22–3×3× the single-junction error rate over a 4-step cascade, not exponentially. This is the benefit of threshold regeneration (Section 4.3): each cycle restores the signal to a clean ternary state before feeding the next. Without regeneration, analog accumulation over 4 steps would amplify errors by a factor of σ×4=2σ× 4=2σ on each side — an exponentially degrading margin. With regeneration, the compounding is linear in cycle count rather than multiplicative. What the simulation does not cover. The simulation is behavioral, not circuit-level. It does not model transistor dynamics (the 10 ns cycle estimate is a timing budget, not a SPICE result), long-term resistance drift (months to years), write endurance (106–109 cycles for RRAM, not a concern for yearly-update knowledge bases), or full-chapter integration beyond the respiratory subset. These are acknowledged as open items for tape-out validation (§7.4). Simulation figure omitted: Error rate vs. device variability at SNR = 20 dB. Left: per-state single-junction error. Right: 4-step cascade error. Dashed line marks the nominal operating point. 6. Comparison: CDC Chip vs. Neural Accelerator for Medical Reasoning Aspect Neural Memristive Accelerator CDC Reasoning Chip What one junction means A weight (fragment, no meaning alone) A clinical assertion (complete, self-contained) Reading one junction gives you One term of a dot product One clinical answer Domain scoping Impossible at hardware level Physical array isolation Typed inheritance Not applicable Meta-gated inter-array paths Cross-axis linkage Not applicable Cross-reference registers Consistency checking Requires full inference + external logic Read-before-write on same array Transitive classification Requires multi-layer + activation + softmax Cascade reads within array Precision per junction 4–8 bits (16–256 levels) 1.58 bits (3 levels) Read circuit Precision ADC Two-threshold comparator Three-valued logic Not representable Native For ICD-11 respiratory diseases ~10M junctions (embeddings) ~136K junctions (assertions) Auditability Post-hoc explanation methods Each junction’s address IS the evidence 7. Discussion 7.1. What Is New Here Not ternary computing (Knuth, 1959; Soviet Setun, 1958). Not in-memory computing (Hu et al., 2018). Not memristive logic (Borghetti et al., 2010). Not TCAM (Pagiamtzis & Sheikholeslami, 2006). Not hyperdimensional in-memory computing (Karunaratne et al., 2020). What is new: A structural homomorphism between a materialized CDC domain algebra and a crossbar topology, with an explicit treatment of bridges. Prior memristive computing maps numerical values to resistance states — the physical layout carries no algebraic meaning. HDC maps vector components to junctions — meaning is distributed. TCAM stores match patterns in flat arrays — entries can be rearranged arbitrarily. This work maps an entire algebra (Heyting lattice with typed Galois connections, established in Paper 2, together with cross-fiber bridges introduced in Paper 3) to a crossbar topology where the wiring IS the algebra. The specialization order is the chip’s inter-array connectivity. The meet is a topological common ancestor. The typing function, unfolded across inheritance edges, drives meta-controlled gates. Bridges across non-comparable fibers are cross-reference registers. The closure property is the physical idempotence of re-running inheritance. None of these structural correspondences exist in neural crossbars, HDC arrays, or TCAMs. 7.2. The Deeper Observation Every computing architecture since von Neumann assumes that storage and computation require different physical mechanisms. Memory cells store; logic gates compute; buses connect them. Even "in-memory computing" only partially addresses this: memristive crossbars compute matrix products in memory, but interpretation, control flow, and decision logic remain external. CDC’s domain algebra suggests why this separation persists: prior data formats do not natively encode computational semantics. A 16-bit floating-point weight of 0.7324 carries no inherent semantic meaning — three identical weights in three different networks compute three different things. A ternary state of +1 at position (CA40.00, is_a, Pneumonia) in the @Anatomical array carries the same meaning no matter what chip it is printed on. The position, the domain, the relation, and the ternary value together fix the semantics; no interpretive layer is needed. When the data format is natively computational, the storage-computation separation dissolves — not just in theory (Paper 3), but in physics (this paper). 7.3. A Broader Structural Reading The homomorphism Φ admits a broader reading. The C-R@D-C’ form is not unique to CDC: it appears in branching control flow (state → transition@condition → state), in abstract syntax trees, in state-transition machines, and in Kripke accessibility structures. Whether these constitute parallel instantiations of a common structural form, or merely share surface notation, is beyond the scope of this paper. We note only that the storage-computation dissolution demonstrated here in hardware is consistent with the software-layer result of Paper 3, suggesting the dissolution may not be substrate-specific. A characterization of what substrate properties suffice to support the C-R@D-C’ form — and the conditions under which storage-computation separation reemerges — is left for future work. 7.4. Limitations Domain-specific. This chip performs domain-constrained classification and reasoning. It does not do general-purpose computation, neural inference, or numerical simulation. Compile-time materialization. The domain structure is fixed at fabrication. Runtime evolution of the domain lattice itself is not supported; software-level mechanisms that split or merge domains must generate a new materialization, which maps to a new chip (or a reconfigurable platform — not pursued here). For stable reference standards such as ICD-11 that update on yearly cycles, this boundary is acceptable; for fast-changing knowledge, it is a real limitation. Static knowledge within each materialization. Reprogramming junctions requires write pulses. For rapidly changing assertions within a fixed domain structure, write endurance becomes relevant. A practical update protocol: freeze the chip during inference; batch-apply standard updates at fixed intervals; version the meta-array to roll back if inconsistency is detected. State drift. RRAM and PCM devices exhibit resistance drift over months to years. A +1 junction drifting toward RmidR_mid converts a clinical assertion to "undefined" rather than flipping it to the opposite truth value — as noted in §5.4, this is the safe failure direction for medical applications, since the system flags an unanswerable query rather than returning a silently incorrect one. Mitigation: periodic readout-and-refresh cycles; ECC across redundant fiber copies. Interconnect area overhead. The claim that "the wiring is the algebra" commits the design to routing an irregular domain lattice directly onto 2D silicon metal layers. For the respiratory-chapter scale (47 arrays, tens of thousands of inter-array wires) this is tractable, but as the number of domains grows toward full ICD-11 (~500 domains) or beyond, irregular inter-array routing will dominate both floorplan area and critical-path delay — the dense 1T1R arrays become a small fraction of total silicon. Future scaled designs will likely need to map inter-array connections onto a programmable Network-on-Chip (NoC) fabric or a shared-bus arbitration layer with routing tables held in SRAM, trading pure topological mapping for spatial efficiency. The homomorphism Φ would then hold up to a fixed routing indirection — a structurally unchanged but physically more realistic implementation. Proof-of-concept scale. The design covers one ICD-11 chapter. Full deployment requires multi-chip integration or larger monolithic arrays, and — as above — likely a NoC-based inter-array fabric. No SPICE validation. This paper provides a behavioral simulation (Section 5.4) but not transistor-level SPICE. The 10 ns cycle estimate is a timing budget, not a verified circuit simulation. Read-margin under process corners, sense-amplifier offset characterization, buffer-tree skew, and parasitic RC extraction on the inter-array wiring all remain to be characterized before tape-out. 8. Conclusion We presented a memristive chip design grounded in a structural homomorphism Φ between a materialized CDC domain algebra (Li, Wang & Zhao, 2026b) and a crossbar topology. The homomorphism preserves fiber isolation as array isolation, the specialization order as directed wiring, meet and Heyting implication as topological properties, ternary valuation as three resistance states, the typed Galois connection (after unfolding τ over inheritance edges) as meta-controlled gates, cross-fiber bridges as cross-reference registers, and the closure property as physical idempotence. This homomorphism is what separates the design from ternary memory. A TCAM stores values in a flat structure where physical layout is arbitrary. The CDC crossbar topology IS the domain algebra — the wiring encodes the specialization order, the gates encode the typing function, the registers encode the bridges, and rearranging connections changes reasoning semantics. This is not a chip that stores medical knowledge. This is a chip whose physical structure is medical knowledge. Five reasoning capabilities — domain scoping, three-valued logic, transitive classification, typed inheritance, and write-time consistency checking — follow as direct consequences of the homomorphism, with cross-axis queries handled by bridge register lookups. Each is physically realized: array isolation prevents cross-domain leakage; three resistance states encode holds/negated/undefined; a row-column cascade circuit within each 1T1R array computes transitive closure; meta-gates control selective inheritance; read-before-write checks consistency; cross-reference registers implement bridges. Behavioral simulation at the nominal operating point (σlog=0.15 _ =0.15, SNR = 20 dB) observes zero errors across all six capabilities in 100,000 trials each, with a safety margin extending to σlog≈0.25 _ ≈ 0.25 before any errors appear — a margin that comfortably accommodates commercial RRAM device variability. The fabrication requirements are modest: three resistance states per junction (vs. 16–256 for neural accelerators), 1T1R cells (standard), two-threshold comparators (vs. precision ADCs), a small SRAM bank for bridges, and ~136,000 memristive junctions for the respiratory chapter. The broader implication: the storage-computation separation that has defined computing architecture since von Neumann persists because prior data formats do not carry algebraic structure. When the data representation has algebraic structure — as CDC’s domain Heyting algebra does — that structure can be materialized into physical topology at compile time, and the separation dissolves. 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