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A Time-Based Readout for Vector-Matrix Multiplication in Fully Analog Memristive SNNs
Elia Mateu-Barriendos, Álvaro Gómez-Pau, Josep Rius, Daniel Arumí, Rosa Rodríguez-Montañés, Salvador Manich
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Status: succeeded | Model: Gemma-4-26B-A4B | Prompt: intel-v1 | Confidence: 95%
Last extracted: 9/12/2026, 1:58:56 AM
Summary
This paper proposes a fully analog readout architecture for Spiking Neural Networks (SNNs) using memristive crossbar arrays. Instead of conventional current-mode sensing, the system employs a voltage-to-time (V2T) conversion circuit that transforms the column voltage resulting from vector-matrix multiplication (VMM) into a pulse duration. This approach reduces area and power overhead associated with current-mode summing and scaling circuitry. The architecture was validated through post-layout simulations of a 10x1 SNN prototype in 130 nm CMOS technology, demonstrating significant area reduction compared to current-sensing schemes, and applied to a 64x10 SNN for digit classification to prove feasibility.
Entities (8)
Relation Signals (7)
Voltage-to-Time (V2T) Readout → usedin → Spiking Neural Network (SNN)
confidence 97% · This work proposes a readout circuit based on a voltage-to-time conversion of the VMM output for fully analog SNN.
Memristive Crossbar Array → performs → Vector-Matrix Multiplication (VMM)
confidence 96% · they inherently perform vector–matrix multiplications (VMMs)
Voltage-to-Time (V2T) Readout → replaces → Current-mode sensing
confidence 95% · By avoiding current-mode readout and explicit scaling circuitry, the approach enables compact neuron design
Voltage-to-Time (V2T) Readout → improves → Area efficiency
confidence 94% · improving area and energy efficiency... achieving ~20x area reduction over a representative current-sensing implementation
Voltage-to-Time (V2T) Readout → improves → Energy efficiency
confidence 93% · improving area and energy efficiency... comparable energy efficiency
1T1R Synapse → implements → Memristive Crossbar Array
confidence 92% · Memristive devices are attractive NVM candidates... and are commonly used in 1T1R configurations.
Digit Classification → validatedby → 64x10 SNN
confidence 90% · application to a trained 64x10 SNN for digit classification further demonstrates its feasibility
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Abstract
Abstract:Artificial neural networks rely on vector-matrix multiplications (VMMs), whose implementation in von Neumann architectures is dominated by costly data movement between memory and processing units. Spiking neural networks (SNNs) mitigate this bottleneck by performing in-memory, analog VMMs using memristive crossbar arrays. However, conventional current-mode readout circuits incur significant area and power overhead. This work proposes a fully analog readout architecture based on voltage-to-time conversion of the VMM output. By sensing the column voltage, the proposed approach avoids current-mode summing and scaling circuitry, improving area and energy efficiency. Post-layout simulations of a 10x1 SNN implemented in a 130 nm CMOS technology validate the proposed architecture, while application to a trained 64x10 SNN for digit classification further demonstrates its feasibility for SNN inference.
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- Source: https://arxiv.org/abs/2609.11713v1
- Canonical: https://arxiv.org/abs/2609.11713v1
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A Time-Based Readout for Vector-Matrix Multiplication in Fully Analog Memristive SNNs Elia Mateu-Barriendos, Álvaro Gómez-Pau, Josep Rius, Daniel Arumí, Rosa Rodríguez-Montañés, Salvador Manich Affiliation: Universitat Politècnica de Catalunya - BarcelonaTech (UPC) Abstract Artificial neural networks rely on vector–matrix multiplications (VMMs), whose implementation in von Neumann architectures is dominated by costly data movement between memory and processing units. Spiking neural networks (SNNs) mitigate this bottleneck by performing in-memory, analog VMMs using memristive crossbar arrays. However, conventional current-mode readout circuits incur significant area and power overhead. This work proposes a fully analog readout architecture based on voltage-to-time conversion of the VMM output. By sensing the column voltage, the proposed approach avoids current-mode summing and scaling circuitry, improving area and energy efficiency. Post-layout simulations of a 10×110 -2.0mu× -2.0mu1 SNN implemented in a 130 nm130\,nm CMOS technology validate the proposed architecture, while application to a trained 64×1064 -2.0mu× -2.0mu10 SNN for digit classification further demonstrates its feasibility for SNN inference. Index Terms: Spiking neural networks (SNNs), Memristor, Synapse, Neuromorphic Hardware, In-memory computing I Introduction Inspired by the human brain, neuromorphic computing aims to emulate the event-driven and distributed processing of biological neural networks. In this paradigm, spiking neural networks (SNNs) encode information as discrete events in time (spikes), enabling asynchronous operation and improved energy efficiency when implemented in hardware [1, 2]. Crossbar arrays are a promising architecture for hardware SNNs [3], where synaptic weights are stored as conductances of non-volatile memory (NVM) devices. By exploiting Ohm’s and Kirchhoff’s laws, they inherently perform vector–matrix multiplications (VMMs), typically sensed as column currents (Fig. 1). Memristive devices are attractive NVM candidates due to non-volatility, multilevel programmability, and CMOS compatibility, and are commonly used in 1T1R configurations. Fig. 1: An SNN with 1T1R memristive synapses employing current-mode crossbar sensing. The VMM output is represented by a column current IREAD,jI_READ,j. While crossbar arrays enable compact in-memory VMMs, overall area and energy efficiency depends strongly on the neuron and readout design [4]. Digital neuron approaches require per-column transimpedance amplifiers and ADCs [5], leading to high area and energy consumption, or time-multiplexed ADCs [6], which reduce area at the cost of throughput. Analog neurons integrate column current on a capacitor, enabling low-power operation. However, scalability is limited by the large read currents. Metal-oxide memristive devices typically operate in the tens to hundreds of kΩk [7], resulting in column currents in the µA A−-mAmA range for large arrays. Obtaining appropriate integration times then requires either large capacitances or additional readout circuitry, or restricting synaptic weights to binary values [8]. Conventional solutions rely on opamp-based readout [9] and current scaling circuits [10], which may also be required in digital schemes [5, 11]. However, these circuits often dominate area and power, and large scaling factors over wide dynamic ranges require complex multi-stage designs [12]. These limitations motivate alternatives to current-mode sensing. Voltage-sensing schemes have been used in compute-in-memory systems [13], while time-based encoding has been implemented in digital architectures [14, 15]. However, these approaches are not directly suited to analog SNNs. This work proposes a readout circuit based on a voltage-to-time conversion of the VMM output for fully analog SNN. By avoiding current-mode readout and explicit scaling circuitry, the approach enables compact neuron design, multi-level weights, and improved area and energy efficiency. This paper is organized as follows. Section I presents the proposed architecture. Section I describes the 10×110 -2.0mu× -2.0mu1 SNN prototype in 130 nm130\,nm CMOS and reports post-layout results. I Voltage-to-time readout architecture Fig. 2 shows the proposed fully analog memristive SNN architecture. Spiking inputs and output neurons are connected through 1T1R synapses, with weights encoded in the conductance GijG_ij. The VMM output is the column conductance ∑iXiGij _iX_iG_ij (with Xi∈0,1X_i∈\0,1\), sensed as a voltage VREAD,jV_READ,j. Fig. 2: Analog SNN with 1T1R memristive synapses employing voltage-mode crossbar sensing. The VMM output is represented by a column voltage VREAD,jV_READ,j and converted into a pulse duration Δtj _j controlling the neuron current injection. A reference current IREFI_REF is injected into each column, selected to keep VREAD,jV_READ,j below the SET voltage. Memristors share a common top electrode, so the current is distributed among active devices, yielding: VREAD,j=IREF∑iXiGij.V_READ,j= I_REF _iX_iG_ij. (1) where the ON-resistance of the access transistor is neglected. The proposed voltage-to-time (V2T) readout circuit converts the column voltage into a variable-width pulse. The circuit receives VREAD,jV_READ,j and a global enable SPK_EN, which is low while any input spike is present. The output signal CTRL is an active-low pulse with duration Δtj _j. Fig. 3 shows a high-level schematic and representative waveforms. (a) Conceptual schematic of the V2T circuit and the IF neuron. Capacitor discharge through an NMOS transistor implements the voltage-to-time conversion, while the OR gate produces the variable-width pulse that injects current into the neuron. For simplicity, the j subscript is omitted. (b) Representative waveforms showing the timing relationship between the input spike XiX_i, SPK_EN, VREADV_READ, VCAPV_CAP, DELAY, and CTRL for a fixed VREADV_READ. Fig. 3: V2T circuit: (a) high-level conceptual schematic including the IF neuron (b) illustrative waveforms. The voltage-to-time conversion is implemented by modulating the discharge time of capacitor CCAPC_CAP. During SPK_EN, capacitor CCAPC_CAP discharges through NMOS M1. After SPK_EN, PMOS M0 restores VCAPV_CAP. The discharge time required for VCAPV_CAP to reach the inverter threshold VTH,I1V_TH,I1 is: Δtj=CCAP⋅ΔVCAPICAP,j _j= C_CAP· _CAPI_CAP,j (2) with ΔVCAP=VDD−VTH,I1 _CAP=V_D-V_TH,I1. Assuming transistor M1 operates in saturation, the capacitor discharge current ICAP,jI_CAP,j follows the alpha-power-law. To ensure saturation, M1 is driven by a scaled and offset version of VREAD,jV_READ,j so that VGS,j=kOF⋅VREAD,j+VOFV_GS,j=k_OF·V_READ,j+V_OF. Therefore, ICAP,jI_CAP,j can be expressed as: ICAP,j∝((kOF⋅VREAD,j+VOF)−VT)αI_CAP,j ((k_OF·V_READ,j+V_OF)-V_T)^α (3) Combining (1), (2) and (3), the relation between the pulse duration Δtj _j and the column conductance ∑iXiGij _iX_iG_ij is obtained: Δtj∝CCAP⋅ΔVCAP((kOF⋅IREF∑iXiGij+VOF)−VT)α _j C_CAP· _CAP ((k_OF· I_REF _iX_iG_ij+V_OF)-V_T )^α (4) Equation (4) describes the resulting conductance-to-time conversion, which is monotonic but inherently non-linear, following a power-law dependence of Δtj _j on ∑iXiGij _iX_iG_ij. Through circuit tuning, a locally approximately linear region can be achieved, as shown in the next section. CTRL is generated by OR-ing SPK_EN with the inverted capacitor voltage. As a result, the capacitor discharge time Δtj _j sets the pulse width (neglecting gate delays). The IF neuron (Fig. 3a) incorporates a switched current source IPOSI_POS controlled by CTRL. The charge injected into the neuron is therefore proportional to the pulse duration Δtj _j: ΔQj=IPOS⋅Δtj _j=I_POS· _j (5) Since the VMM output is encoded in time, IPOSI_POS can be set by neuron design constraints. This contrasts with current-sensing schemes, where the VMM result is encoded in the current amplitude and scales with the column output. I Results and Discussion A 10×110 -2.0mu× -2.0mu1 SNN prototype based on the architecture in Fig. 2 was implemented in 130 nm130\,nm CMOS and submitted for fabrication. The layout is shown in Fig. 4 and design parameters are summarized in Table I. Fig. 4: Layout of the implemented 10×110 -2.0mu× -2.0mu1 SNN prototype. Total area is 2880.52 µm22880.52\, m^2. TABLE I: Design parameters for the 10×110 -2.0mu× -2.0mu1 SNN prototype Parameter Value Description GijG_ij 0.1 mS–1 mS0.1\,mS1\,mS Memristor conductance W/LW/L 3.9 µm3.9\, m/0.13 µm0.13\, m 1T1R access transistor VREADV_READ 2.5 mV–250 mV2.5\,mV250\,mV Column voltage IREFI_REF 25 µA25\, A Column current reference CCAPC_CAP 60 fF60\,fF V2T capacitor CMEMC_MEM 66.5 fF66.5\,fF Neuron membrane capacitor CFBC_FB 47.5 fF47.5\,fF Neuron feedback capacitor IPOSI_POS 25 nA25\,nA Neuron charging current INEGI_NEG 40 nA40\,nA Neuron discharging current The V2T circuit is designed for input spikes with 2.5 µs2.5\, s pulse width at rates up to 200 kHz200\,kHz. The scaling and offset network is implemented using diode-connected MOS transistors, sized to draw negligible current compared to active memristors so that the read operation is not disturbed. The IF neuron operates on the input spikes timescale. All current sources are implemented using conventional CMOS current source structures. Robustness was verified through PVT corners and Monte Carlo simulations, with σ/μ=σ/μ=13.7 %13.7\,\% timing spread at the maximum-conductance operating point under combined process and mismatch variations. I-A Post-layout simulation results This subsection presents post-layout simulation results of the 10×110 -2.0mu× -2.0mu1 SNN prototype. The memristive devices are simulated using the Verilog-A model available in the PDK [16]. Fig. 5 shows the pulse duration Δtj _j as a function of the column conductance ∑iXiGij _iX_iG_ij, obtained from a representative subset of active inputs and conductance combinations. From Fig. 5, it is confirmed that the relation in (4) is monotonic, enabling time-based representation of the VMM output over the operating range. The inset shows the approximately linear region, while saturation at higher conductance reflects the underlying power-law dependence. At high column conductance, additional simultaneously active inputs reduce the sensitivity of the conversion rather than preventing circuit operation. Fig. 5: Post-layout simulation results of the conductance-to-time conversion characteristic of the 10×110 -2.0mu× -2.0mu1 SNN prototype. Fig. 6: Post-layout simulation waveforms of the 10×110 -2.0mu× -2.0mu1 SNN prototype, illustrating two scenarios: one (orange) and ten (blue) simultaneously active inputs at 200 kHz200\,kHz, corresponding to column conductances of 0.2 mS0.2\,mS and 2 mS2\,mS, respectively. Fig. 6 shows representative circuit waveforms for one and ten simultaneously active inputs at 200 kHz200\,kHz and 0.2 mS0.2\,mS synaptic weights. The resulting column voltage modulation produces distinct CTRL pulse durations, leading to neuron firing rates of 11.8 kHz11.8\,kHz and 66.8 kHz66.8\,kHz, respectively. I-B Area and Energy Table I reports the layout area of the implemented prototype (excluding access circuitry), also expressed in equivalent minimum-size inverters (7.56 µm27.56\, m^2). TABLE I: Area of the Implemented Prototype Sub-circuit Area [µm2 m^2] Area [INV] 10×110 -2.0mu× -2.0mu1 1T1R synapses 393393 5252 V2T circuit 480480 63.563.5 IF Neuron 11601160 153.5153.5 Total 20332033 269269 Energy is evaluated at the level of the synaptic circuit (including the reference current generator) and the V2T circuit. The 10×110 -2.0mu× -2.0mu1 synaptic circuit draws 42.8 µA42.8\, A independently of input activity, resulting in 128.5 pJ128.5\,pJ per read operation over 2.5 µs2.5\, s. The V2T circuit draws 10.3 µA10.3\, A in idle and 0.19 µA0.19\, A during conversion, yielding 0.58 pJ0.58\,pJ per operation. The total energy per synaptic operation (synaptic readout plus voltage-to-time conversion) is 129 pJ129\,pJ. Area and idle power scale approximately linearly with the number of output neurons, as each requires one IREFI_REF current generator and one V2T circuit. However, ∼ 70% of the V2T circuit area is occupied by decoupling capacitors, which can be shared in larger systems. Idle power can be reduced by disabling the IREFI_REF current generator when no input is active. I-C Comparison with a current-sensing scheme As a representative example of a current-sensing readout, [10] employs an opamp-based input stage and a current-scaling circuit providing 500×500× attenuation. The per-column readout area in 130 nm130\,nm CMOS, estimated from an optical micrograph, occupies 11 000 µm211\,000\, m^2 (≈1455≈ 1455 INV), over 20×20× larger than the proposed V2T circuit. The power per read operation reported in [10] is 48 µW48\, W, corresponding to 120 pJ120\,pJ over our 2.5 µs2.5\, s time window. While this energy is of the same order of magnitude, [10] considers a current range of 10 µA–200 µA10\, A200\, A. These currents correspond to a column conductance of 0.04 mS–0.8 mS0.04\,mS0.8\,mS (at 250 mV250\,mV), which is <10%<10\% of the 0.1 mS–10 mS0.1\,mS10\,mS range targeted here. Using a current-sensing scheme, our 10×110 -2.0mu× -2.0mu1 SNN would produce column currents from 25 µA25\, A to 2.5 mA2.5\,mA. Scaling these to the nAnA-range would require attenuation factors of 10310^3–10510^5 and additional circuitry to enforce a fixed read voltage, which would increase the energy of 120 pJ120\,pJ by several orders. I-D Application to Digit Recognition To further evaluate the proposed approach, a 64×1064 -2.0mu× -2.0mu10 SNN was trained in software on the Digit dataset [17] using back-propagation, with synaptic weights constrained to be non-negative. The trained weights were quantized to ten conductance levels spanning the memristor range (1 kΩ to 10 kΩ1\,k 10\,k ) and mapped to a schematic-level implementation, where the IF analog neurons were extended with leakage (implemented as a constant current source) and lateral inhibition. Representative 8×88 -2.0mu× -2.0mu8 digit samples, rate-encoded over 100 µs100\, s, produced the same classification outcome in both the software-trained network and the circuit implementation (Fig. 7), providing preliminary validation of the proposed architecture in a trained SNN inference task. Fig. 7: Application of the proposed architecture to a trained 64×1064 -2.0mu× -2.0mu10 SNN with quantized synaptic weights. Membrane traces are included only when multiple neurons are active. IV Conclusion This work proposes a time-based readout circuit for fully analog SNNs with memristive synapses. The proposed approach converts the VMM output, sensed as a column voltage, into a time-domain signal that controls neuron current injection. By avoiding current-mode readout, the approach eliminates complex, area-intensive circuitry that becomes challenging at high column currents. A 10×110 -2.0mu× -2.0mu1 SNN prototype with the proposed architecture was implemented in 130 nm130\,nm CMOS. Post-layout results confirm correct conductance-to-time conversion, achieving ∼ 20× -2.0mu× -2.0mu area reduction over a representative current-sensing implementation with comparable energy efficiency. Application to a trained 64×1064 -2.0mu× -2.0mu10 SNN further demonstrates the feasibility of the architecture for inference with quantized memristive weights. Acknowledgment This work has been supported by PID2022-141391OB-C22 funded by MCIN/AEI/10.13039/501100011033/FEDER, UE. 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