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Edge Physical AI Deployment of Vision Transformers on Heterogeneous Edge GPU Targeting Autonomous Vehicles
Ashiyana Abdul Majeed, Mahmoud Meribout, Neethu Joseph, Abel Kidane Haile, Mohammad Abdullah Al Faruque
Intelligence
Status: succeeded | Model: Gemma-4-26B-A4B | Prompt: intel-v1 | Confidence: 91%
Last extracted: 7/18/2026, 1:42:48 PM
Summary
This paper introduces Heterogeneous Frame Dispatch Scheduling (H-FraDS), a methodology for deploying Vision Transformers (specifically Swin Transformer) on heterogeneous edge GPUs like the NVIDIA Jetson AGX Orin. The approach addresses hardware incompatibilities by adapting transformer components (reshaping tensors, approximating ERF with tanh, replacing LayerNorm) to run on Deep Learning Accelerators (DLA). H-FraDS routes frames across GPU and dual DLA cores using fixed dispatch ratios to optimize latency and power efficiency. The system achieves 125.93 FPS with a 2.36x speedup over standalone DLA execution, maintaining 92% of the original F1 score, and integrates an Optical Flow Accelerator (OFA) for enhanced perception.
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H-FraDS â achievesperformance â 125.93 FPS
confidence 95% · H-FraDS Balanced Dispatch (1:2) achieves 125.93 FPS
H-FraDS â runson â NVIDIA Jetson AGX Orin
confidence 95% · H-FraDS routes frames across the GPU and dual deep learning accelerator (DLA) cores... on a recent NVIDIA edge GPU.
H-FraDS â optimizes â Swin Transformer
confidence 92% · Using Swin Transformer for autonomous-driving perception, H-FraDS Balanced Dispatch (1:2) achieves 125.93 FPS
Swin Transformer â targets â Autonomous Vehicles
confidence 90% · Using Swin Transformer for autonomous-driving perception
Swin Transformer â uses â Deep Learning Accelerator (DLA)
confidence 90% · H-FraDS routes frames across the GPU and dual deep learning accelerator (DLA) cores
H-FraDS â integrates â Optical Flow Accelerator (OFA)
confidence 88% · Optical flow accelerator (OFA) is further used for inference-side optical-flow estimation... GPU-DLA-OFA case
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Abstract
Abstract:Physical AI systems, such as autonomous vehicles and intelligent machines, require transformer-based perception models that satisfy stringent edge latency and energy constraints. However, heterogeneous edge-GPU deployment remains limited by underutilized hardware engines and accelerator-incompatible operators, causing fragmented execution and lower throughput per watt. This paper presents Heterogeneous Frame Dispatch Scheduling (H-FraDS), a hardware-aware frame scheduling methodology for transformer inference on a recent NVIDIA edge GPU. H-FraDS routes frames across the GPU and dual deep learning accelerator (DLA) cores using fixed dispatch ratios to improve utilization under latency and power constraints. To enable scheduling, incompatible transformer components are adapted for DLA execution by reshaping tensors, approximating error function (ERF) with tanh, and replacing layer normalization with bounded tanh. The adapted model maintains a 92% F1 score, with only a 2% reduction from the original. Optical flow accelerator (OFA) is further used for inference-side optical-flow estimation. To the best of the authors' knowledge, prior work has not addressed these combined issues. Using Swin Transformer for autonomous-driving perception, H-FraDS Balanced Dispatch (1:2) achieves 125.93 FPS, a 2.36x speedup over standalone adapted-DLA execution, 4.0 FPS/W, and approximately 24 ms DLA latency, satisfying 30 FPS real-time operation; the GPU-DLA-OFA case achieves a 2.02x DLA throughput speedup.
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- Source: https://arxiv.org/abs/2607.10942v1
- Canonical: https://arxiv.org/abs/2607.10942v1
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DNN deep neural network GAN generative adversarial network GNN graph neural network CNN convolutional neural network DLA deep learning accelerator PVA programmable vision accelerator VIC video image compositor SSD single shot detector GPC graphics processing cluster SM streaming multiprocessors DMA direct memory access VLIW very long instruction word VPU vector processing unit TPU tensor processing unit VPI Vision Programming Interface AxoNN energy-aware execution of neural networks HaX-CoNN heterogeneity aware execution of concurrent deep neural networks D-HaX-CoNN dynamic heterogeneity aware execution of concurrent deep neural networks CP-CNN computational parallelization for CNNs PCCS processor-centric contention-aware slowdown model PND partial network duplication SMT satisfiability modulo SAT satisfiability LP linear programming Jedi Jetson-aware embedded deep learning inference RNN recurrent neural network GA genetic algorithm H2H heterogeneous model to heterogeneous system mapping MaGNAS mapping-aware graph neural architecture search AI-SoC AI-System-on-Chip LLM large language models RL Reinforcement Learning PSNR peak-signal-to-noise ratio SSIM structural similarity ratio MSE mean-square error MRI magnetic resonance imaging CT computed tomography NPU neural processing unit FPGA field programmable gate array ASIC application specific integrated circuit DSP digital signal processor PET positron emission tomography OCT optical coherence tomography GELU Gaussian error linear unit LRN local response normalization VLA vision-language-action model VLM vision language model FSD full self-driving ERF error function MLP multilayer perceptron YOLO you only look once VGG visual geometry group ViT Vision Transformer DVFS dynamic voltage and frequency scaling EMC external memory controller AV autonomous vehicle OFA optical flow accelerator H-FraDS Heterogeneous Frame Dispatch Scheduling Edge Physical AI Deployment of Vision Transformers on Heterogeneous Edge GPU Targeting Autonomous Vehicles Ashiyana Abdul Majeed, Mahmoud Meribout, Neethu Joseph, Abel Kidane Haile, and Mohammad Abdullah Al Faruque Ashiyana Abdul Majeed, Dr. Mahmoud Meribout, Neethu Joseph, and Abel Kidane Haile are with the Department of Computer and Information Engineering, Khalifa University, Abu Dhabi, UAE (email: 100059454@ku.ac.ae, mahmoud.meribout@ku.ac.ae, 100069410@ku.ac.ae, ku100053692@alumni.ku.ac.ae). Dr. Mohammad Abdullah Al Faruque is with the Department of Electrical Engineering and Computer Science at the University of California, Irvine, CA 92697, USA (email: alfaruqu@uci.edu). Abstract Physical AI systems, such as autonomous vehicles and intelligent machines, require transformer-based perception models that satisfy stringent edge latency and energy constraints. However, heterogeneous edge-GPU deployment remains limited by underutilized hardware engines and accelerator-incompatible operators, causing fragmented execution and lower throughput per watt. This paper presents Heterogeneous Frame Dispatch Scheduling (H-FraDS), a hardware-aware frame scheduling methodology for transformer inference on a recent NVIDIA edge GPU. H-FraDS routes frames across the GPU and dual deep learning accelerator (DLA) cores using fixed dispatch ratios to improve utilization under latency and power constraints. To enable scheduling, incompatible transformer components are adapted for DLA execution by reshaping tensors, approximating error function (ERF) with tanh , and replacing layer normalization with bounded tanh . The adapted model maintains a 92% F1 score, with only a 2% reduction from the original. is further used for inference-side optical-flow estimation. To the best of the authorsâ knowledge, prior work has not addressed these combined issues. Using Swin Transformer for autonomous-driving perception, H-FraDS Balanced Dispatch (1:2) achieves 125.93 FPS, a 2.36Ă speedup over standalone adapted-DLA execution, 4.0 FPS/W, and â 24 ms DLA latency, satisfying 30 FPS real-time operation; the GPU-DLA- optical flow accelerator (OFA) case achieves a 2.02Ă DLA throughput speedup. Index Terms: deep learning accelerator (DLA), transformer networks, Heterogeneous Frame Dispatch Scheduling (H-FraDS), heterogeneous computing, optical flow accelerator (OFA), autonomous driving, embedded vision systems, edge AI I Introduction Modern edge-AI systems must execute real-time perception and signal-processing workloads under strict latency, power, and thermal constraints. Applications such as autonomous driving, mobile robotics, intelligent surveillance, industrial inspection, and embedded vision increasingly rely on compact heterogeneous platforms that combine GPU resources with fixed-function engines, including deep learning accelerators (DLAs), vision accelerators, video engines, and optical-flow engines. Their practical performance, therefore, depends not only on model accuracy but also on whether the deployment pipeline can exploit the available hardware engines concurrently [4]. Autonomous driving is a representative high-pressure case: perception must support detection and localization under varied environmental conditions within tight computational budgets, since latency or accuracy failures can propagate to prediction, planning, and control. This creates a central trade-off among accuracy, latency, and efficiency, particularly as high-performing models become more computationally demanding. This work is motivated by the transition from conventional edge AI to edge physical AI, where perception models are no longer isolated classifiers but foundational components inside closed-loop physical agents. In physical AI systems, visual backbones support perception, mapping, tracking, planning, and action selection under real-time constraints. Therefore, the deployment question is not only whether a transformer model is accurate, but whether it can operate continuously on an embedded heterogeneous AI-System-on-Chip (AI-SoC) within a fixed power envelope. NVIDIA Jetson AGX Orin is a representative platform for this setting because it combines GPU compute, dual DLA engines, OFA, high-bandwidth shared memory, and a robotics-oriented software stack [17]. In this context, hardware-aware transformer adaptation and the H-FraDS scheduler provide the system mechanism for efficiently executing foundational visual perception blocks at the edge. Previously, convolutional neural networks served as the dominant paradigm for visual perception. Architectures such as ResNet [9], visual geometry group (VGG) [33], and you only look once (YOLO) [28] demonstrated strong performance on standard benchmarks. However, the locality of convolution limits the receptive fieldâs growth with depth, making it difficult to model global context and long-range interactions between objects [25], properties critical in complex traffic environments. Achieving full autonomy also requires integrating transformer-based architectures alongside convolutional models for more effective multi-sensor data fusion [37]. Transformer-based models are increasingly attractive for edge perception because they model long-range dependencies and global context. The Vision Transformer (ViT) [8] demonstrated that treating images as sequences of fixed-size patches processed through a standard transformer encoder could match or exceed CNN accuracy on large-scale image classification. Despite this, ViTâs global self-attention at a fixed resolution produces a single-scale feature map poorly suited to the multi-scale requirements of object detection and dense prediction, and its quadratic complexity with respect to image resolution is prohibitive for high-resolution automotive cameras [22]. The Swin Transformer [22] addressed both limitations through a hierarchical architecture with shifted-window self-attention, yielding linear complexity and a multi-scale feature pyramid well-matched to autonomous-driving and embedded-vision perception tasks. Modern edge AI platforms integrate dedicated DLA engines alongside GPU cores to enhance inference efficiency. A growing body of work addresses edge-aware deployment of ViT through quantization, pruning, knowledge distillation, scheduling, and hardware-software co-design [29, 14]. Scheduling techniques such as Map-and-Conquer [5] demonstrate that transformer workloads can benefit from heterogeneous mapping across GPU and DLA resources. However, they generally assume that the model layers are already compatible with the selected hardware engine [27]. This assumption is restrictive for hierarchical vision transformers, where unsupported operators and tensor layouts can trigger GPU fallback before scheduling can provide its intended benefit. This work addresses that gap by combining transformer compatibility adaptation with hardware-engine-aware scheduling, following the broader hardware-aware deployment philosophy of prior convolutional-model implementations [26]. The main contributions are as follows: âą General accelerator-aware transformer deployment methodology. A systematic methodology is presented for deploying transformer-based edge-AI models on heterogeneous edge-GPU platforms by combining accelerator-compatibility adaptation with hardware-engine-aware scheduling. The methodology is demonstrated on the Swin Transformer using the latest NVIDIA edge GPU platform for autonomous-driving perception. However, the substitutions apply to transformer architectures that share the same structural incompatibilities. Together, these modifications reduce GPU fallback transitions and improve subsequent scheduling across available hardware engines. âą Maximum hardware-engine exploration with first frame dispatch scheduling. Five scheduling strategies are designed, implemented, and benchmarked on the recent NVIDIA edge GPU, covering free-running concurrent task execution, single-DLA frame dispatch, dual-DLA interleaved dispatch, symmetric dual-DLA operation, and concurrent GPU-DLA-OFA execution. To the best of the authorsâ knowledge, this is the first work to explore frame-based dispatch scheduling on powerful edge GPU platforms such as the NVIDIA Jetson, and the first to integrate the OFA as an active concurrent inference unit within a heterogeneous scheduling framework for transformer-based perception. The framework was implemented and evaluated for the first time in urban, crowded road scenes in Abu Dhabi, UAE, to support autonomous-vehicle perception. âą Latency and power-efficiency analysis against automotive driving requirements. Per-frame DLA perception latency and system-level throughput per watt are reported and evaluated against three automotive latency thresholds: real-time 30 FPS (†33 ms), urban driving (†50 ms), and highway driving (†100 ms). I Related Work Edge physical AI requires embedded agents to perform perception, reasoning, and action under strict latency, power, memory, and thermal constraints. In this setting, the visual backbone serves as a foundational perceptual block for downstream tasks, including detection, tracking, mapping, forecasting, and planning. Vision transformers are attractive for this role because they capture long-range spatial context. However, their deployment on Jetson-class edge AI-SoC platforms requires both accuracy preservation and hardware compatibility. This motivates the proposed Swin Transformer adaptation and H-FraDS scheduler, which connect transformer model design with the heterogeneous GPU, dual-DLA, and OFA resources of NVIDIA Jetson AGX Orin. I-A Transformer-Based Autonomous Driving Perception Pipelines The adoption of transformer-based architectures in autonomous driving perception has accelerated significantly following the success of ViT [8] and its hierarchical successors on standard vision benchmarks [22], alongside the broader real-time object-detection and hardware-acceleration literature for autonomous vehicles [30]. The core appeal of transformers for autonomous driving lies in their ability to model long-range dependencies and global context across the full sensor field of view, properties critical when reasoning about spatially distant but semantically related objects. This has driven their adoption not only as image feature extractors but also as the backbone of unified perception, prediction, and planning frameworks [37]. Among hierarchical transformer backbones, the Swin Transformer [22] has emerged as the de facto standard for multi-scale visual perception in autonomous driving, owing to its linear complexity, shifted-window cross-region interaction, and multi-resolution feature pyramid. UniAD [12] uses a Swin-T backbone to feed a cascade of task-specific transformer modules covering tracking, mapping, motion forecasting, occupancy prediction, and ego-motion planning, demonstrating that a single hierarchical encoder can simultaneously serve multiple heterogeneous perception tasks. SparseDrive [34] similarly adopts a Swin backbone within a sparse instance query framework, exploiting its multi-resolution feature pyramid for efficient scene representation. The recurrence of hierarchical vision transformers across these systems underscores that their efficient deployment on embedded AI-SoC hardware, specifically with full DLA compatibility, is a critical prerequisite for practical autonomous driving, which is precisely the problem this work addresses. I-B Edge-Aware Implementations of Transformer Models Prior work has explored the deployment of vision transformer models across a range of edge hardware platforms, employing strategies such as operator approximation, mixed-precision quantization, and hardware-software co-design to bridge the gap between transformer architecture requirements and the constraints of fixed-function accelerators [24, 1], with recent FPGA-focused surveys extending this discussion to transformers, VLMs, CNN-based detection, classification, and tracking [32, 31]. A notable example targeting the Swin Transformer specifically is [24], which proposes an field programmable gate array (FPGA)-based accelerator for the Swin Transformer targeting edge computing applications such as autonomous driving and face recognition, where real-time inference is critical. The primary challenge lies in adapting computationally expensive operations, namely layer normalization, softmax, and Gaussian error linear unit (GELU), to fixed-point FPGA logic. To address this, layer normalization is replaced with batch normalization, which can be used with preceding linear layers at inference time, eliminating the need for per-sample mean and variance computation. The softmax function is approximated by substituting the natural exponential exe^x with a base-2 power 2x2^x, yielding: Softmaxâ(xi)â2xiâxmaxâj2xjâxmaxSoftmax(x_i)â 2^x_i-x_ _j2^x_j-x_ (1) This reformulation reduces exponentiation to hardware-efficient bit-shift and addition operations. The GELU activation is similarly approximated using a sigmoid-based form: GELUâ(x)âxâ Ïâ(1.702âx)GELU(x)â x·Ï(1.702\,x) (2) where Ïâ(â )Ï(·) denotes the sigmoid function, avoiding the need for hyperbolic tangent or Gaussian cumulative distribution function evaluation. All linear operations, including convolutions and matrix multiplications, are unified by a single matrix-multiplication unit operating on a 16-bit fixed-point datapath. Against a CPU baseline (AMD Ryzen 5700X), the accelerator achieves a 1.25Ă1.25Ă speedup on Swin-B (base model of Swin Transformer), with energy efficiency gains of 14.63Ă14.63Ă over the CPU and 3.00Ă3.00Ă over an NVIDIA RTX 2080 Ti GPU, at the cost of lower raw throughput (0.12Ă0.12Ă that of the GPU). The substitution of layer normalization with batch normalization incurs a 0.7%0.7\% accuracy loss on Swin-B, which the authors consider acceptable given the efficiency gains [24]. Map-and-Conquer [5] takes a complementary approach by partitioning AI models horizontally along the width dimension into concurrent sub-networks, which are then dispatched across heterogeneous compute units such as GPU and DLA cores. Applied to the Visformer vision transformer [6] on the NVIDIA Jetson AGX Xavier, the scheduler reduces energy consumption by 14%14\% and latency by 43%43\% relative to DLA-only execution, while preserving model accuracy. However, Map-and-Conquer assumes full layer compatibility with the target hardware and does not handle DLA-incompatible layers. This limits its applicability to more complex architectures such as the Swin Transformer, where certain layers cannot be efficiently mapped to DLA cores without additional adaptation. I Background I-A Hardware Architecture The NVIDIA Jetson AGX Orin was considered in this paper as it incorporates the same fundamental heterogeneous computing components found in many modern edge AI platforms, including multi-core ARM CPUs, a high-performance GPU, and dedicated accelerators, all sharing a unified memory subsystem. The Orin device combines multi-core ARM CPUs, an Ampere-based GPU, dual DLA engines, and additional multimedia accelerators such as the programmable vision accelerator (PVA), video image compositor (VIC), and OFA, all interconnected through a shared memory subsystem. I-A1 GPU The Orin GPU is an Ampere-architecture device with two graphics processing clusters, each containing 8 streaming multiprocessorss with 128 CUDA cores and 64 Tensor Cores, delivering up to 170 Sparse TOPS [17]. I-A2 DLA The DLA is a fixed-function accelerator designed for energy-efficient CNN inference, comprising a convolution core, data processors, dedicated memory, and reshape engines [13]. Its integration within an edge GPU platform is architecturally significant. By executing structured, computationally intensive operations such as convolutions and pooling, the DLA frees GPU resources for more complex, irregular computations, thereby enabling heterogeneous parallel execution. This capability is particularly important in autonomous driving and other edge-AI applications, where multiple perception and decision-making tasks must execute concurrently under stringent power and thermal constraints. Furthermore, the DLA typically delivers significantly higher performance per watt than the GPU for convolution-dominated workloads, making it an attractive execution target for compatible portions of deep neural networks. Consequently, there has been growing interest in scheduling and partitioning AI workloads across the DLA and GPU to maximize system throughput and energy efficiency [27]. However, several hardware constraints limit the direct deployment of transformer-based models on the DLA [19]. Supported precisions are restricted to FP16 and INT8, tensors must be four-dimensional, activation functions are limited to ReLU, Sigmoid, TanH, Clipped ReLU, and Leaky ReLU, and neither GELU activations nor large matrix multiplications are natively supported. Operators that violate these constraints are automatically offloaded to the GPU, resulting in execution fragmentation, reduced concurrency, and lower overall throughput. The term DLA-targeted execution is used throughout this paper to indicate TensorRT deployment with the DLA selected as the primary execution engine. Unsupported operations may still execute via TensorRT-managed GPU fallback; therefore, the objective of the proposed adaptation is to reduce, rather than eliminate, fallback-induced fragmentation. CameraFrameTransformerOperator Adaptation3D â 4DTensor Layouterfâtanherfâ â bounded tanh -targeted EngineH-FraDSFrame DispatcherGPUSwin framesDLA0/DLA1Swin framesOFAOptical FlowPhysical-AI OutputsLatency, FPS, FPS/W DLA compatibility loop Figure 1: Proposed edge physical AI deployment pipeline. A hardware-aware Swin Transformer processes incoming camera frames, compiled using TensorRT and executed through the H-FraDS dispatcher, which routes frames across GPU, DLA0, DLA1, and OFA pipelines according to the selected dispatch ratio. I-A3 OFA The OFA is a fixed-function engine for optical flow and stereo disparity [17]. In this work, optical flow mode is used: the OFA accepts an externally built image pyramid (scale factor 2, up to five levels) and outputs per-block S10.5 motion vectors at grid sizes of 1Ă11Ă1 to 8Ă88Ă8 pixels, achieving 1.13 ms latency at 1920Ă10801920Ă1080 with 8Ă8 grid size [16]. I-B Transformer Architecture The transformer architecture was originally introduced by Vaswani et al. [35] for sequence-to-sequence tasks in natural language processing. Its core building block is the self-attention mechanism, which computes pairwise relationships between all elements in a sequence. Given an input sequence of n tokens, each represented as a d-dimensional vector, the mechanism projects the input into queries Q, keys K, and values V via learned linear projections, and computes attention as: Attentionâ(,,)=Softmaxâ(â€dk)âAttention(Q,K,V)=Softmax\! ( QK d_k )V (3) where dkd_k is the dimension of the keys. Multiple attention heads are computed in parallel and concatenated (Multi-head Self-Attention, MSA), enabling the model to capture relationships at different representation subspaces simultaneously [35]. Each transformer block pairs MSA with a two-layer multilayer perceptron (MLP) using GELU activation [10], with layer normalization [2] applied before each sub-layer following the pre-norm convention. The ViT [8] adapted this architecture to image data by splitting the input image into a sequence of fixed-size non-overlapping patches, linearly projecting each patch into a token embedding, and appending a learnable classification token. A stack of standard transformer encoder blocks processes the resulting sequence. While ViT demonstrated competitive accuracy on large-scale image classification, its global self-attention over a fixed-resolution sequence produces a single-scale feature map and scales quadratically with image resolution, both of which are significant limitations for dense prediction tasks and high-resolution automotive cameras. Hierarchical vision transformers address these limitations by introducing multi-scale feature extraction and local attention. Rather than computing attention globally, attention is restricted to local spatial windows, reducing the complexity from quadratic to linear with respect to image size. Cross-window interactions are recovered through a shifted-window mechanism that alternates the window partition between successive blocks [22]. Patch merging layers downsample the spatial resolution between stages while increasing channel depth, producing a multi-scale feature pyramid analogous to a CNN backbone and well-suited to object detection and semantic segmentation. This design has become the dominant backbone for autonomous driving perception frameworks [12, 34, 37, 23]. Three structural properties are shared across this family of architectures and are directly responsible for DLA incompatibility. First, the self-attention module naturally produces intermediate tensors of the form (BatchĂSequenceĂChannel)(BatchĂSequenceĂChannel), a 3D layout incompatible with the DLAâs fixed 4D addressing scheme. Second, the GELU activation [10] relies on the error function (ERF) function, which is not a natively supported primitive on the DLA. Third, layer normalization [2] requires dynamic per-sample computation of mean and variance, operations that the DLA cannot execute. Together, these three incompatibilities force GPU fallback at multiple points in the pipeline, fragmenting execution and reducing the energy efficiency benefit of the accelerator. The methodology proposed in Section IV addresses each incompatibility in turn and is demonstrated on the Swin Transformer [22], a representative hierarchical vision transformer that exhibits all three. IV Suggested Methodology IV-A Hardware Accelerator-Aware Model Fig. 1 summarizes the proposed native system view, replacing generic architecture diagrams with the complete edge physical AI deployment flow from camera input to operator adaptation, TensorRT compilation, heterogeneous frame dispatch, and platform-level efficiency measurement. To produce a DLA-compatible variant of a vision transformer, each model stage must be systematically analyzed to identify operations and tensor formats incompatible with the DLAâs hardware constraints. For each identified incompatibility, a functionally equivalent or mathematically approximated substitute is applied to ensure that the modified model can execute as a continuous DLA pipeline with minimal GPU fallback. This methodology is extended here and applied to transformer architectures, following the broader hardware-aware deployment philosophy of prior convolutional-model implementations [26]. The challenge of hardware-efficient execution of transformer operations, including large matrix multiplications, nonlinear activations, and normalization layers, has been studied from the FPGA perspective in [36, 1, 24]. This work addresses the similar incompatibilities from the DLA perspective on an edge AI-SoC. The following subsections detail each incompatibility class identified in the Swin Transformer, together with its corresponding substitution. The same substitutions apply to any transformer architecture exhibiting these structural patterns. IV-A1 3D Format The DLA requires all input and intermediate tensors to conform to a 4D format, represented as either (BatchĂChannelĂHeightĂWidth)(BatchĂChannelĂHeightĂWidth) or (BatchĂHeightĂWidthĂChannel)(BatchĂHeightĂWidthĂChannel) depending on the data layout convention [19]. This is a fundamental hardware limitation, as the DLAâs memory-addressing circuitry is physically designed for 4D spatial feature maps and lacks an addressing mode for 3D tensors [13]. It cannot be resolved through software or driver updates; the memory controller does not support the addressing pattern required by a 3D tensor. Within the transformerâs self-attention module, intermediate tensors of the form (BatchĂSequenceĂChannel)(BatchĂSequenceĂChannel) are naturally produced [22] and are therefore structurally incompatible with this hardware requirement. Without modification, these operations fall back to the GPU, necessitating the insertion of additional shuffle layers at the DLA-GPU boundaries to resize tensors between the two formats for each transition. To eliminate this overhead, all 3D tensors were reshaped into their 4D equivalents by reintroducing the spatial dimensions prior to DLA execution. This ensures that tensor operations remain within the supported format throughout inference, removing the need for GPU fallback at these layers. As a direct consequence, the number of shuffle layers required across the pipeline was reduced, resulting in more continuous DLA execution and improved overall inference efficiency. Figure 2: Left: comparison of erfâ(x)erf(x) and tanhâĄ(x) (x), illustrating their close agreement. Right: the resulting GELU activation computed with each formulation, showing a negligible difference between the erf-based original and the tanh -based approximation used in the proposed model. IV-A2 GELU The GELU activation function can be expressed using Equation 4 [10]. The root cause of its DLA incompatibility is the presence of the ERF function, which is absent from the DLAâs natively supported primitive set [19]. This is primarily a hardware limitation, as the DLA implements activation functions as fixed lookup tables or dedicated arithmetic units, and the ERF function, which requires evaluating a Gaussian integral, is not among the operations supported by the DLAâs hardware. This is not a software stack deficiency that could be resolved with a driver or compiler update; the physical compute units needed to evaluate ERF are not present. As shown in Equation 5, the ERF function can be closely approximated using tanh [10]. GELUâ(x)=x2â[1+erfâ(x2)] (x)= x2 [1+erf\! ( x 2 ) ] (4) erfâ(x)=2Ïââ«0xeât2âtâtanhâĄ(2Ïâ(x+0.044715âx3)) (x)= 2 Ï _0^xe^-t^2dtâ \! ( 2Ï (x+0.044715x^3 ) ) (5) In our implementation, the ERF within the GELU activation was directly replaced with the tanh function for simplicity, as the tanh is natively supported by the DLA as a standard activation function [19]. This targeted substitution preserves the overall structure of GELU while eliminating the unsupported ERF operation, allowing the activation function to remain DLA-targeted with reduced fallback. The resulting approximated GELU is given in Equation 6. GELUâ(x)=x2â[1+tanhâĄ(x2)] (x)= x2 [1+ \! ( x 2 ) ] (6) The GELU substitution is motivated by the standard tanh-form approximation of the Gaussian cumulative distribution used in transformer implementations. Unlike the exact ERF-based expression, the tanh-based form maps directly to a DLA-supported activation primitive. The approximation preserves the smooth gating behavior of GELU while avoiding unsupported transcendental operations. Figure 3: Effect of layer normalization and the tanh approximation on an example feature vector drawn from â(2, 1.52)N(2,\,1.5^2) (inset), and output range as a function of the input mean ÎŒ (main). IV-A3 Layer Normalization Layer normalization, introduced by [2], is applied throughout the Swin Transformer after each attention block and MLP block [22]. Equation 7 represents the operation, where ÎŒ and Ï2Ï^2 are the mean and variance computed across the feature dimension of the input, ϔΔ is a small constant added for numerical stability, and Îł and ÎČ are learned affine parameters [2]. Layer normalizationâ(x)=xâÎŒÏ2+Ï”â Îł+ÎČ normalization(x)= x-ÎŒ Ï^2+Δ·γ+ÎČ (7) The DLA does not support the dynamic computation of mean and variance, nor the square root and division operations required by layer normalization [19]. This is again a hardware limitation as these operations require data-dependent, per-sample arithmetic that the DLAâs fixed-function pipeline cannot perform â unlike a GPU, which executes arbitrary compute shaders, the DLA has no programmable execution units capable of computing running statistics. This cannot be resolved at the software or compiler level, as no amount of graph optimization can map dynamic normalization onto hardware that physically lacks the required arithmetic capability. This forces these layers to be executed on the GPU, resulting in pipeline fragmentation. To improve DLA-targeted execution, layer normalization was substituted with a tanh -based approximation, which is natively supported. While tanh does not replicate the exact normalization behavior of layer normalization [2], it provides a bounded, smooth non-linearity that can partially compensate for the distribution shift that layer normalization would otherwise correct. (a) Concurrent Task Scheduling. YOLOv8 runs on the GPU and Swin Transformer on the DLA in free-running, independent threads with no shared dispatch clock. (b) Multi-Accelerator Scheduling. YOLOv8, Swin Transformer, and Dense Optical Flow run concurrently on the GPU, DLA, and OFA, respectively, in independent free-running threads. Figure 4: Timing diagrams for free-running concurrent scheduling strategies. The LayerNorm substitution is not an algebraic equivalence. Instead, it is a deployment-oriented bounded surrogate introduced to preserve stable activation ranges under DLA constraints. LayerNorm performs three functions: centering, variance normalization, and learned affine rescaling. The proposed bounded tanh surrogate primarily preserves the range-stabilization function, while sacrificing exact per-sample centering and variance normalization. This design choice is justified only when the resulting accuracy degradation remains acceptable after calibration or fine-tuning, as verified experimentally by the F1-score comparison. To quantify the approximation effect, operator-level activation deviation can be measured as Îact=1Mââi=1M|yiorigâyisub|. _act= 1M _i=1^M |y_i^orig-y_i^sub |. (8) This metric separates operator-level approximation error from end-task accuracy degradation and provides a direct way to analyze the effect of the substitution. In this work, the end-to-end F1 degradation remains limited to 2.65 percentage points, suggesting that the substituted model preserves most task-relevant representations. TABLE I: Theoretical comparison between LayerNorm and the bounded tanh surrogate. Property LayerNorm Bounded tanh surrogate Mean handling Explicit per-sample centering No explicit centering Variance handling Explicit per-sample scaling Range compression Output range Unbounded after affine parameters Bounded to [â1,1][-1,1] before later scaling DLA support Unsupported dynamic statistics, division, and square root Supported activation primitive Interpretation Statistical normalization Hardware-feasible activation stabilization For clarity, Table I summarizes the theoretical difference between exact LayerNorm and the proposed bounded surrogate. The surrogate should be interpreted as a hardware-feasible stability mechanism rather than as a replacement with identical statistics. LayerNorm maps each token feature vector to a normalized affine space using data-dependent mean and variance. The bounded tanh surrogate instead compresses activations into [â1,1][-1,1], limiting outliers and reducing dynamic-range variation before DLA execution. This is useful for fixed-function inference because bounded activations reduce the probability of large intermediate values that amplify quantization and scheduling sensitivity. Consequently, the validity of the substitution is established empirically rather than by algebraic equivalence. The proposed model is acceptable only if the task-level accuracy drop remains bounded and the deployment benefit is significant. This is why the paper reports both the F1-score reduction and the throughput/latency/FPS-per-watt improvement, and why an operator-ablation table is included to isolate the contribution of each transformation. IV-B DLA-Aware Scheduling Strategies After compatibility adaptation, the scheduling stage evaluates how the available hardware engines can be used concurrently rather than treating the DLA as an isolated execution target. Deploying the DLA-compatible Swin Transformer on the Jetson AGX Orin in isolation exploits only one of the platformâs inference-capable accelerators. To fully leverage the heterogeneous compute fabric, GPU, dual DLA cores, and OFA, this work designs and evaluates five scheduling strategies that distribute incoming perception frames or concurrent workloads across these units. The strategies are listed as follows: free-running concurrent execution, free-running multi-accelerator execution, free-running dual-DLA symmetric execution, single-DLA H-FraDS, and dual-DLA interleaved H-FraDS. In the timing diagram, the hatched regions indicate periods during which the hardware unit is idle, waiting for the next frame to arrive. In free-running strategies (Naive, Dual DLA, OFA), no frame pacing is applied, and units loop at the hardwareâs fastest rate. IV-B1 Free-Running Concurrent and Multi-Accelerator Scheduling In the simplest configuration, separate inference tasks are assigned to individual accelerators and executed in independent threads with no shared dispatch clock. A YOLOv8 model runs on the GPU while the Swin Transformer runs on a single DLA core, each looping at its own hardware-limited rate. An extended variant adds a dense optical flow model on the OFA, creating a three-way concurrent pipeline. These strategies maximize individual accelerator utilization but do not coordinate frame arrival, and the DLAâs throughput is limited by the per-inference latency of the transformer model. The timing diagrams for these free-running strategies are shown in Fig. 4. As neither the GPU nor the DLA units are paced, both loops continuously: the GPU completes YOLOv8 inference in â 4 ms cycles, while the DLA processes Swin Transformer frames at â 20 ms intervals in the proposed model. The absence of coordination means that any latency improvement from reducing DLA inference time directly translates into a proportional throughput gain, without introducing idle periods. Figure 5: Timing diagram for Dual DLA scheduling. Two Swin Transformer instances run on DLA core 0 and DLA core 1, respectively, in independent free-running threads. IV-B2 Free-Running Symmetric Dual-DLA Scheduling A symmetric dual-DLA configuration runs two independent Swin Transformer instances on DLA0 and DLA1 in parallel, doubling raw DLA throughput without GPU involvement. Because no explicit GPU inference task is launched, any observed GPU utilization in this mode is entirely due to GPU-fallback operations within the TensorRT DLA engines. The timing diagram for the Dual-DLA configuration is shown in Fig. 5. Both DLA cores execute independently and symmetrically, with no inter-core synchronization. Since no GPU inference task is scheduled, the GPU remains idle except for DLA-fallback operations. The diagram illustrates that the two engines operate in near lock-step, confirming the symmetric hardware behavior observed in the results. Frame arrivesCompute FrameID mod N set by chosen scheduling ratioSingle or DualDLA mode?Single-DLA FrameDispatch SchedulingDual-DLA InterleavedFrame DispatchFrameIDmod N = 0?FrameIDmod N = 0or 1?DLA0GPUDLA0 or DLA1Detection outputNoNoYesYes Figure 6: Flowchart of the H-FraDS frame dispatch strategy. (a) 1:1 (Alternating Frame). Both units finish well before the next frame arrives. (b) 1:2 (Balanced Dispatch). DLA latency (â 20 ms) â 2Ă GPU latency (â 9 ms) â best-balanced ratio. (c) 1:3 (GPU-Dominant). GPU becomes the bottleneck (3Ă9 ms >> 20 ms), leaving the DLA idle â 7 ms per cycle. (d) 1:5 (DLA-Sparse). DLA finishes at â 20 ms, but the next DLA frame does not arrive until 200 ms into the cycle. Figure 7: Timing diagrams for single-DLA H-FraDS strategies. Block widths are proportional to per-frame latencies; hatched regions indicate idle periods. IV-B3 H-FraDS: Single-DLA and Dual-DLA Frame Dispatch H-FraDS is the central contribution of this scheduling analysis. Rather than running each accelerator independently, a shared dispatch controller monitors incoming frames and routes them deterministically to either the DLA or the GPU based on a fixed ratio N:(Nâ1)(N-1) (DLA:GPU). Every N-th frame in the sequence is forwarded to the DLA core; the remaining Nâ1N-1 frames per cycle are dispatched to the GPU. This design exploits the latency asymmetry between the two accelerators: the DLA is slower per inference but energy-efficient, while the GPU is faster but power-hungry. By selecting a ratio that matches the hardware latency balance, both units can remain simultaneously busy with minimal idle time. The flowchart in Fig. 6 illustrates the H-FraDS routing logic. Four single-DLA ratios are evaluated: 1:1 (Alternating Frame), 1:2 (Balanced Dispatch), 1:3 (GPU-Dominant), and 1:5 (DLA-Sparse). Two dual-DLA variants extend this to route two consecutive frames, one to DLA0 and one to DLA1, per N-th cycle, at ratios 2:2 and 2:3. (a) 2:2 ratio. DLA0 receives frameIdmod4=0frameId 4=0; DLA1 receives frameIdmod4=1frameId 4=1; remaining frames go to the GPU. Both DLA cores run concurrently. (b) 2:3 ratio. DLA0 receives every 5th frame, and DLA1 receives the subsequent frame; the remaining three frames per cycle go to the GPU. Both DLA cores run concurrently. Figure 8: Timing diagrams for dual-DLA interleaved H-FraDS. The timing diagrams for the four single-DLA ratios are shown in Fig. 7. The 1:1 ratio (Fig. 7a) illustrates that both units finish well before the next frame arrives, leaving significant idle time on both hardware units. As the ratio increases to 1:2 (Fig. 7b), the DLA latency (â 20 ms) is approximately twice the GPU latency (â 9 ms), achieving near-optimal simultaneous saturation of both units. The same scheduling scheme can also be extended to include OFA, enabling concurrent execution across multiple hardware engines, as illustrated in Fig. 9. At 1:3 (Fig. 7c), the GPU becomes the bottleneck, processing three consecutive frames (3Ă9â273Ă 9â 27 ms) while the DLA finishes earlier and idles for â 7 ms per cycle. At 1:5 (Fig. 7d), the DLA-Sparse configuration leaves the DLA substantially underutilized: after completing its inference at â 20 ms, the next DLA frame does not arrive until 200 ms into the cycle. The timing diagrams for the dual-DLA interleaved strategies are shown in Fig. 8. In the 2:2 ratio (Fig. 8a), DLA0 and DLA1 each receive one frame per four-frame cycle, running concurrently while the GPU handles the remaining two frames. In the 2:3 configuration (Fig. 8b), the GPU handles three frames per cycle while both DLA cores together handle two, providing a larger GPU share and a more GPU-dominant balance. The optimal ratio is model-dependent and is determined by the relative per-inference latencies of the DLA and GPU engines. For the proposed model, the DLA inference time (â 20 ms) is approximately twice the GPU inference time (â 9 ms), which predicts that the 1:2 Balanced Dispatch ratio will saturate both units simultaneously, a prediction confirmed experimentally in Section V. For the original model, whose DLA latency (â 115 ms) is far higher than the GPUâs, routing more frames to the GPU monotonically improves total throughput. This illustrates that the optimal dispatch ratio must be re-evaluated whenever architectural modifications alter the per-inference latency balance, thereby directly motivating the evaluation of both model variants across all nine experiments. To the best of the authorsâ knowledge, H-FraDS is the first frame-level dispatch scheduling strategy to route transformer inference frames across GPU and dual-DLA engines on Jetson-class edge GPU platforms. Figure 9: Balanced Dispatch (1:2) with OFA execution in parallel. Figure 10: Qualitative inference results using OFA and the proposed models on daytime road scenes in Abu Dhabi, UAE, across three representative frames. V Experimental Results and Discussion V-A Assessment on Dataset The primary models were trained and evaluated on the Roboflow Udacity object classification dataset [15], which provides an autonomous-driving perception benchmark for comparing the original and hardware-aware Swin Transformer variants. For this dataset, the F1 score, the harmonic mean of precision and recall, was used as the primary accuracy metric. The proposed model achieves an F1 score of 92.26%, compared to 94.91% for the original model, with an 11.7% improvement in DLA-targeted throughput on the Roboflow Udacity input configuration. The reduction in F1 score is an expected consequence of the architectural substitutions introduced to improve DLA compatibility, since these substitutions introduce approximation error during inference. Nevertheless, the proposed model retains most of the original modelâs discriminative capability, indicating that the hardware-aware modifications preserve the core representational capacity of the Swin Transformer. To evaluate generalization beyond a single training and validation source, additional experiments were conducted using KITTI and Cityscapes. These datasets were not used with identical task formulations. KITTI was used for evaluation in road/lane bounding-box detection, where the F1 score quantifies detection and localization quality. Cityscapes was used for training and evaluation in a 19-class semantic segmentation task, where pixel accuracy is an appropriate dense-prediction metric. Therefore, the dataset-level results in Table I report the metric corresponding to each datasetâs implemented task. The purpose of these additional experiments is not to claim state-of-the-art accuracy on KITTI or Cityscapes, but to verify that the proposed DLA-compatibility substitutions do not overfit to the Roboflow Udacity distribution. Throughput is reported for the measured deployment configuration associated with each dataset: Roboflow Udacity uses the DLA-targeted execution configuration, while KITTI and Cityscapes use GPU execution. TABLE I: Dataset-level validation and throughput comparison. Udacity uses DLA-targeted execution; KITTI and Cityscapes use GPU execution. Dataset Metric Val. (%) FPS Orig. Prop. Dev. Orig. Prop. Udacity F1 94.91 92.26 DLA 47.67 53.26 KITTI F1@0.5 100.00 96.55 GPU 260.14 262.80 Cityscapes Pix. Acc. 89.11 84.84 GPU 209.34 199.09 V-B Throughput Performance The inference throughput of both models was measured under a fully DLA-resident execution configuration on the NVIDIA Jetson AGX Orin, where each model is compiled and run entirely on the DLA engine without concurrent GPU inference tasks. Throughput measures the number of frames processed per second, a critical metric for real-time execution pipelines. The corresponding throughput results are included in Table I. The hardware-aware model achieves a throughput of 53.26 FPS, compared to 47.67 FPS for the original model, resulting in an 11% improvement. This gain is attributed to the reduction in unsupported operations that would otherwise require GPU fallback during inference. The proposed model executes a greater proportion of its computation directly on the DLA, reducing the number of GPU-DLA transitions and the associated memory transfer overhead. The removal of shuffle layers, which were previously required at format boundaries, further contributes to the observed throughput improvement. A similar difference is also seen in the GPU execution of the models trained on the KITTI and Cityscapes datasets. TABLE I: Comparison of concurrent and heterogeneous multi-accelerator scheduling Scenario Model GPU Util (%) DLA Util (%) OFA Util (%) GPU FPS DLA FPS OFA FPS Power (W) Concurrent Task Scheduling Original 80.77 31.38 â 232.30 10.47 â 29.04 Proposed 95.68 6.18 â 227.89 19.67 â 36.67 Multi-Accelerator Scheduling Original 97.30 30.50 71.05 222.46 10.26 175.75 33.87 Proposed 98.65 5.64 71.68 235.92 20.74 176.20 41.85 V-C Power and Utilization Measurement Methodology As energy efficiency is a primary constraint in edge physical AI systems, all power measurements in this work are reported at the system level rather than as isolated accelerator power. Measurements were collected using NVIDIA Tegrastats [18] during steady-state inference after an initial warm-up. All experiments were performed at a fixed frequency setting: CPU at 2201 MHz, GPU at approximately 1293-1296 MHz, and DLA at 1600 MHz, with the external memory controller (EMC) running at 3199 MHz. Locking the frequency across experiments removes dynamic voltage and frequency scaling (DVFS) artifacts from the comparison and ensures that observed differences in throughput and power reflect the scheduling architecture rather than operating-point variation. The reported power corresponds to the average platform power during the measurement window, including GPU, DLA, memory system, CPU runtime, and scheduler overheads. GPU, DLA, and OFA utilization are reported as the percentage of time each accelerator remains actively executing inference workloads during the measurement interval. Throughput per watt is computed as ηFPS/W=TotalâprocessedâframesâperâsecondAverageâplatformâpowerâinâwatts. _FPS/W= Total\ processed\ frames\ per\ secondAverage\ platform\ power\ in\ watts. (9) For single-model configurations, the numerator corresponds to the Swin Transformer throughput. For concurrent multi-accelerator configurations, the numerator includes the aggregate throughput of simultaneously active perception tasks, because all active hardware engines share the measured power. This distinction is important: multi-task FPS/W evaluates platform utilization efficiency, whereas single-model FPS/W evaluates the efficiency of a specific model deployment. V-D Heterogeneous Scheduling Experiments To evaluate the throughput and power characteristics of both models under concurrent multi-hardware execution, a set of heterogeneous scheduling strategies was implemented and benchmarked on the NVIDIA Jetson AGX Orin. Timing diagrams for all strategies are presented in Section IV-B. V-D1 Concurrent Task Scheduling (YOLOv8 on GPU and Swin Transformer on DLA) and Multi-Accelerator Scheduling (GPU, DLA, and OFA) In this configuration, a YOLOv8 object detection model runs concurrently on the GPU. In contrast, the Swin Transformer runs on DLA core 0, each in an independent thread with its own event-synchronized inference loop. Table I reports the results under the fixed frequency setting. The proposed model achieves 19.67 DLA FPS, compared to 10.47 FPS for the original, representing an 88% increase in DLA throughput. GPU throughput remains comparable between the two models (232.30 vs. 227.89 FPS), as the YOLOv8 workload is identical in both cases. The lower DLA utilization of the proposed model (6.18% vs. 31.38%) reflects faster per-inference execution: the DLA completes each frame more quickly and spends proportionally less time active. The increase in total power (29.04 vs. 36.67 W) is primarily driven by higher GPU utilization (95.68% vs. 80.77%), resulting from the faster DLA, which releases shared memory resources sooner and allows the GPU to sustain a higher throughput. In the heterogeneous three-task configuration, YOLOv8 runs on the GPU, the Swin Transformer runs on DLA core 0, and a dense optical flow model runs on the OFA hardware accelerator, all concurrently in independent threads. Table I reports the results. The timing diagram is shown in Fig. 4b. The proposed model achieves 20.74 DLA FPS, compared with 10.26 FPS for the original, consistent with the standalone DLA speedup. GPU and OFA throughput are comparable between the two models, as neither the YOLOv8 model nor the optical flow engine changes. Adding the OFA task increases EMC bus contention relative to the naive two-task case, slightly suppressing DLA throughput for both models compared to the standalone Naive Scheduling results. V-D2 H-FraDS: Alternate, Balanced, GPU-Dominant, and DLA-Sparse H-FraDS routes every N-th frame to the DLA and the remaining Nâ1N-1 frames to the GPU per cycle, using the same non-blocking concurrent design. Four ratios were evaluated: 2nd frame (1:1 DLA:GPU), 3rd frame (1:2 DLA:GPU), 4th frame (1:3 DLA:GPU), and 6th frame (1:5 DLA:GPU). Timing diagrams are shown in Fig. 7 in Section IV-B. Table IV reports the utilization and power results for the 3rd, 4th, and 6th frame strategies. To further isolate the parallel OFA-enabled 3rd-frame configuration, Table V summarizes the CPU, GPU, DLA, throughput, and power behavior when H-FraDS runs with OFA execution in parallel. TABLE IV: Utilization and power consumption of H-FraDS strategies Strategy Model GPU DLA Power Util. (%) Util. (%) (W) 2nd Frame Original 32.48 48.08 21.08 Proposed 94.40 16.54 31.30 3rd Frame Original 37.23 49.14 23.23 Proposed 95.93 7.47 31.15 4th Frame Original 45.94 46.36 21.96 Proposed 94.25 4.56 29.40 6th Frame Original 63.24 48.70 24.80 Proposed 94.38 0.30 32.16 TABLE V: 3rd-frame OFA scheduling resource summary Model GPU Util. (%) DLA Util. (%) DLA FPS GPU FPS OFA FPS Power (W) Original 34.68 45.41 17.42 34.84 52.26 24.45 Proposed 93.09 8.32 41.75 83.51 125.26 36.07 Figure 11: Throughput comparison between the different H-FraDS strategies. Across all H-FraDS strategies, total FPS increases with the GPU:DLA ratio for the original model, since the original DLA is the bottleneck (per-inference latency â 115 ms) and routing more frames to the faster GPU raises throughput. For the proposed model, total FPS peaks at the 3rd frame ratio (125.93 FPS) in free-running mode and declines at higher ratios. The proposed modelâs DLA latency (â 20 ms) is close to the GPU latency (â 9 ms), indicating an optimal 1:2 DLA:GPU ratio for equal hardware loading, consistent with the 3rd-frame strategy delivering the highest free-running throughput. At a paced input rate, however, the input frame rate equally limits all H-FraDS strategies, and the choice of ratio affects only the hardware idle distribution rather than total system throughput. In the 2nd-frame H-FraDS strategy, the proposed model achieves 60.37 total FPS vs. 17.35 FPS for the original, a 248% improvement. The low DLA utilization of the proposed model (16.54%) is consistent with its faster per-frame DLA inference, which completes well within the time budget available in each 1:1 cycle. The original model has a higher DLA utilization (48.08%), reflecting the longer per-inference time of the unmodified engine. The total throughput comparison across all single-DLA H-FraDS strategies is shown in Fig. 11. With parallel OFA execution, the 3rd-frame H-FraDS strategy preserves the proposed modelâs throughput advantage and produces results similar to those of the proposed model, achieving 41.75 DLA FPS and 83.51 GPU FPS while maintaining moderate power consumption at 36.07 W. V-D3 Symmetric DLA Scheduling: Two Swin Transformer Instances on DLA0 and DLA1 In this configuration, two independent instances of the Swin Transformer run concurrently, one on each DLA core, without any GPU inference task. Table VI reports the results. The timing diagram is shown in Fig. 5 in Section IV-B. TABLE VI: Symmetric DLA scheduling (Swin on DLA0 and DLA1) Model GPU Util. (%) DLA0 Util. (%) DLA1 Util. (%) DLA0 FPS DLA1 FPS Power (W) Original 57.97 44.07 47.92 15.97 15.95 29.15 Proposed 88.19 15.91 16.17 57.22 57.15 37.60 Both DLA cores show near-identical throughput across models, confirming that the two engines run symmetrically. The proposed model achieves 57.22 and 57.15 FPS on DLA0 and DLA1, respectively, compared to 15.97 and 15.95 FPS for the original, a 3.6Ă improvement per core. Since no explicit GPU task is scheduled, the observed GPU utilization (57.97% original, 88.19% proposed) is entirely due to GPU fallback operations executed within the TensorRT DLA engines. The higher GPU utilization for the proposed model reflects the fact that although the total number of GPU-fallback layers is reduced, the remaining fallback operations are individually more GPU-intensive, as they represent the operations most incompatible with the DLA. TABLE VII: Comparison of dual-DLA interleaved H-FraDS strategies Scenario Model GPU Util. (%) DLA0 Util. (%) DLA1 Util. (%) Power (W) 4th Frame (2:2) Original 66.52 40.34 47.50 32.45 Proposed 82.85 1.52 1.81 36.24 5th Frame (2:3) Original 69.11 48.26 47.51 23.65 Proposed 85.48 0.33 0.98 27.32 Figure 12: Throughput comparison between the different dual DLA scheduling strategies. V-D4 Dual-DLA Interleaved H-FraDS This methodology extends single-DLA H-FraDS. It routes two consecutive frames to DLA0 and DLA1, respectively, per Nth-frame cycle (frameIdmodN=0âDLA0frameId N=0 0; frameIdmodN=1âDLA1frameId N=1 1; remainder âGPU ). Two ratios were tested: 4th (2:2 DLA:GPU) and 5th (2:3 DLA:GPU). Table VII reports the utilization and power results. The timing diagrams are shown in Fig. 8 in Section IV-B. Both ratios offer similar overall throughput, with the 5th-frame strategy yielding 104.04 FPS and the 4th-frame strategy yielding 103.30 FPS (using the proposed transformer model variant). The throughput comparison across the evaluated configurations is summarized in Fig. 12. V-E Latency and Power Efficiency Analysis A critical requirement for any autonomous driving perception system is that inference latency remains within the bounds imposed by the vehicleâs reaction budget. At 30 FPS camera input, the maximum tolerable frame-to-frame latency is 33.3 ms (one frame period). Although ISO 26262 does not mandate fixed perception latency thresholds, automotive perception pipelines are commonly designed around real-time constraints near 30 FPS (â 33 ms). In this work, we additionally evaluate latency regimes relevant to urban driving (†50 ms) and highway driving (†100 ms), corresponding to object displacements of approximately 0.7 m at 50 km/h and 3.6 m at 130 km/h per inference cycle [20]. Figure 13: DLA perception latency (ms/frame) for each scheduling strategy, original and proposed models. Dashed lines mark the real-time 30 FPS threshold (33 ms), the urban AV budget (50 ms), and the highway AV budget (100 ms). Fig. 13 reports the per-frame DLA perception latency (reciprocal of DLA FPS) for every scheduling strategy evaluated in this work. The three automotive thresholds are overlaid as dashed reference lines. For the original model, only the Dual-Core Interleaved (2:3) strategy falls below the 50-ms urban threshold. In comparison, most strategies exceed the 100 ms highway budget, particularly the Concurrent Task and Multi-Accelerator strategies, where DLA latency reaches â 96 ms and â 97 ms, respectively, due to the high per-inference cost of the unmodified engine. The proposed model substantially changes this picture: every single-DLA H-FraDS strategy (Alternating Frame through DLA-Sparse) and both Symmetric DLA configurations achieve latencies below 50 ms, with Balanced Dispatch (1:2) achieving â 24 ms, comfortably within the real-time 30 FPS budget. The Dual-Core Interleaved and Symmetric DLA strategies achieve â 48 ms and â 9 ms, respectively, for the proposed model. Even the Concurrent Task strategy, which operates in free-running mode, achieves â 51 ms with the proposed model, narrowly missing the urban threshold. These results confirm that the proposed DLA-compatible Swin Transformer is suitable for real-time autonomous driving perception across a range of heterogeneous scheduling configurations. In contrast, the original model fails to meet urban or real-time latency budgets across all tested strategies. Figure 14: System throughput per watt (FPS/W) across all scheduling strategies. Higher values indicate better power efficiency. Fig. 14 reports the system-level throughput per watt (FPS/W) for all strategies. The Heterogeneous Multi-Accelerator strategy achieves the highest FPS/W for both models (original: 12.1, proposed: 10.3 FPS/W), as the three concurrent tasks amortize the system power draw across the largest total frame count. Among single-DLA H-FraDS strategies, Balanced Dispatch yields the best FPS/W for the proposed model (4.0 FPS/W), reflecting its near-optimal hardware loading. The Symmetric DLA strategy achieves only 3.0 FPS/W, despite high per-core throughput, because it draws full system power when no GPU inference task is running. The highest aggregate FPS/W is observed in the multi-accelerator configuration because GPU, DLA, and OFA workloads share the same platform power budget. However, this should not be interpreted as the most efficient single-model Swin deployment. Among the H-FraDS single-model dispatch configurations, Balanced Dispatch provides the best latency-efficiency trade-off for the proposed Swin model, achieving â 24 ms latency and 4.0 FPS/W. TABLE VIII: Positioning of the proposed method relative to representative edge-transformer optimization approaches. Method Target Platform Optimization Type Transformer Compatibility Handling Main Difference from This Work Map-and-Conquer [5] Jetson AGX Xavier GPU/DLA Network partitioning and heterogeneous mapping Assumes target layers are accelerator-compatible Improves scheduling after compatibility is available, but does not modify incompatible transformer operators. FPGA Swin accelerator [24] Custom FPGA Hardwareâsoftware co-design Replaces LayerNorm and approximates nonlinear functions Requires a custom accelerator design, whereas this work targets commercial NVIDIA Jetson DLA/GPU/OFA hardware. Compression-based edge ViT methods [29] General edge devices Quantization, pruning, and distillation Usually preserves the original operator graph Reduces model size or arithmetic cost, but may not remove DLA-unsupported operators. Proposed method NVIDIA Jetson AGX Orin GPU/DLA/OFA Operator adaptation and frame-level heterogeneous scheduling Reshapes 3D tensors to 4D, replaces ERF-based GELU, and substitutes LayerNorm with bounded tanh Targets practical edge physical AI deployment on existing heterogeneous AI-SoC hardware. When analyzing the trade-offs, the proposed model strategies lie in the low-latency, moderate-efficiency region (<<50 ms, 2-4 FPS/W). The H-FraDS Balanced Dispatch strategy occupies the most favorable position among the H-FraDS group: 24 ms latency and 4.0 FPS/W efficiency. No original-model strategy achieves both latency <<100 ms and efficiency >>2 FPS/W simultaneously. The proposed model therefore dominates across the latency-efficiency Pareto frontier, making it the preferred configuration for real-time autonomous driving deployments on the NVIDIA Jetson AGX Orin. VI Discussion and Comparison with Other Related Works The results show that transformer-based vision models can be adapted for heterogeneous edge-AI platforms with dedicated DLAs, GPU resources, and OFA. By replacing unsupported operators, restructuring incompatible tensor formats, and exploiting concurrent execution, the proposed methodology improves throughput on commercially available edge hardware. The H-FraDS Balanced Dispatch configuration further improves utilization by distributing frames according to accelerator latency, reducing idle periods, and increasing system throughput. The proposed method differs from prior optimization approaches because it intervenes directly in the deployment stack. Compression methods such as quantization, pruning, and distillation reduce arithmetic cost, but do not necessarily make the graph executable on fixed-function accelerators. Map-and-Conquer improves heterogeneous mapping, but assumes that the selected hardware engine already supports the mapped operators. FPGA-based Swin accelerators jointly modify the algorithm and the hardware but require a custom accelerator fabric. In contrast, this work targets commercial Jetson-class AI-SoCs and combines graph-level compatibility adaptation with frame-level scheduling across GPU, DLA, and OFA. Compared with prior work, this contribution complements edge-AI optimization and transformer-acceleration studies. Quantization and algorithm-level methods improve efficiency on resource-constrained platforms [21], while specialized transformer accelerators accelerate softmax, nonlinear functions, or FPGA-based transformer execution [1, 36, 3]. However, these approaches typically require algorithmic redesign or custom hardware. The proposed methodology instead enables deployment on existing heterogeneous edge-GPU platforms by adapting the neural network architecture to satisfy DLA constraints while maximizing concurrency across available engines. This deployment focus is important for autonomous driving and edge-AI systems, where multiple perception tasks must run simultaneously under latency, power, and thermal constraints [7]. The DLA is attractive because it provides efficient execution for structured inference workloads while freeing the GPU for more complex computations. However, current DLA architectures remain optimized mainly for convolutional workloads, whereas vision transformers include operators such as GELU, LayerNorm, and large matrix multiplications that trigger GPU fallback. Previous heterogeneous-scheduling studies primarily address workload orchestration and resource allocation across accelerators [5, 26, 11, 27]. They generally assume that the target model is already executable on the selected engine. This work addresses the preceding compatibility problem by transforming the model before scheduling, thereby reducing fallback-induced fragmentation and enabling more effective use of GPU, DLA, and OFA resources. Overall, the presented approach bridges the gap between modern transformer architectures and current heterogeneous edge-AI hardware. Rather than relying on custom transformer accelerators, which are not yet widely available in commercial edge-GPU platforms, it adapts transformer models to existing accelerator constraints and schedules them across available engines. This provides a practical pathway for deploying transformer-based perception on embedded AI-SoCs. The proposed operator substitutions are hardware-driven approximations and are not mathematically equivalent to the original Swin Transformer operations. In particular, the bounded tanh surrogate for LayerNorm preserves activation range control but does not reproduce exact per-sample centering or variance normalization. Therefore, the method requires task-level validation after substitution and may require calibration for other transformer architectures or datasets. In addition, power is measured at the platform level, which reflects practical deployment cost but does not isolate per-engine energy consumption. Finally, H-FraDS uses deterministic fixed dispatch ratios; adaptive scheduling based on queue length, thermal state, or power budget could further improve robustness under dynamic workloads. Figure 15: Experimental Setup. VII Conclusion This paper presents an edge physical AI deployment methodology for adapting transformer-based vision models to execute efficiently on heterogeneous NVIDIA Jetson-class AI-SoC platforms, demonstrating it with the Swin Transformer on the Jetson AGX Orin. Three architectural substitutions (4D tensor reshaping, ERF-to-tanh substitution in GELU, and layer normalization replacement with a tanh -based non-linearity) eliminate the DLA-incompatible operations that are structurally common across hierarchical vision transformer architectures, yielding an 11% throughput improvement (47.67 to 53.26 FPS) at a 2.65% F1 score cost on the Roboflow Udacity dataset. Five heterogeneous scheduling strategies were benchmarked across the Jetsonâs GPU, dual DLA cores, and, for the first time, the OFA as an active concurrent inference unit. The H-FraDS Balanced Dispatch (1:2) experiment achieves 125.93 FPS, a 2.5Ă gain over standalone DLA operation, by matching the dispatch ratio to the hardware latency balance. All nine experiments meet the 50 ms urban driving budget with the proposed model, and three satisfy the 33 ms real-time threshold, with H-FraDS Balanced Dispatch identified as the Pareto-optimal point at 24 ms and 4.0 FPS/W. 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