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Formal Foundations for Known Good Reliable Die Screening in Chiplet-Based AI Systems-on-Chip
Prashanthi Metku, Chandra Gandu
Intelligence
Status: succeeded | Model: Gemma-4-26B-A4B | Prompt: intel-v1 | Confidence: 91%
Last extracted: 7/23/2026, 3:10:36 AM
Summary
This paper formalizes a transition from Known Good Die (KGD) to Known Good Reliable Die (KGRD) screening for chiplet-based AI SoCs. It introduces a Bayesian probabilistic risk model to map pre-assembly telemetry to post-assembly failure likelihood, addressing the 'observability gap' where package-induced stress factors are unmeasurable pre-assembly. Key contributions include a safety-gated decision architecture with provable failure probability guarantees, uncertainty-aware disposition boundaries derived from Bayes-optimal decision theory, and a constrained closed-loop feedback mechanism that corrects for survivorship bias in model updates. Monte Carlo simulations on synthetic data verify the theoretical properties.
Entities (8)
Relation Signals (5)
Known Good Die → contrastswith → Known Good Reliable Die
confidence 95% · Existing Known Good Die (KGD) screening guarantees pre-assembly functional correctness, yet it offers no probabilistic assurance of post-assembly reliability lifetime.
Safety-Gated Decision Architecture → providesguaranteefor → Known Good Reliable Die
confidence 92% · a safety-gated decision architecture that provides a provable post-assembly failure probability guarantee
Bayesian Probabilistic Risk Model → addresses → Observability Gap
confidence 90% · The risk model maps pre-assembly telemetry to post-assembly failure likelihood with a quantified observability bias bound.
Monte Carlo Simulation → verifies → Bayesian Probabilistic Risk Model
confidence 88% · A Monte Carlo simulation study on N = 4,000 synthetic dies verifies all four theoretical properties
Closed-Loop Feedback Mechanism → corrects → Survivorship bias
confidence 85% · a constrained closed-loop feedback mechanism that delivers consistent model improvement without violating reliability constraints... survivorship bias problem
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Abstract
Abstract:The rapid growth of chiplet-based artificial intelligence systems-on-chip (SoCs) has exposed a fundamental gap in semiconductor test methodology. Existing Known Good Die (KGD) screening guarantees pre-assembly functional correctness, yet it offers no probabilistic assurance of post-assembly reliability lifetime. To address this limitation, the present work formalizes the transition from KGD to Known Good Reliable Die (KGRD) screening as a constrained inference problem over incomplete pre-assembly observability. Building upon this formulation, four interlocking contributions are presented: (i) a Bayesian probabilistic risk model that maps pre-assembly telemetry to post-assembly failure likelihood with a quantified observability bias bound; (ii) a safety-gated decision architecture that provides a provable post-assembly failure probability guarantee; (iii) uncertainty-aware disposition boundaries derived from Bayes-optimal decision theory; and (iv) a constrained closed-loop feedback mechanism that delivers consistent model improvement without violating reliability constraints. A Monte Carlo simulation study on N = 4,000 synthetic dies verifies all four theoretical properties and confirms that the safety guarantee holds uniformly across the full range of tested gate threshold.
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- Source: https://arxiv.org/abs/2607.20141v1
- Canonical: https://arxiv.org/abs/2607.20141v1
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Formal Foundations for Known Good Reliable Die Screening in Chiplet-Based AI Systems-on-Chip Prashanthi Metku, Chandra Gandu Abstract The rapid growth of chiplet-based artificial intelligence systems-on-chip (SoCs) has exposed a fundamental gap in semiconductor test methodology. Existing Known Good Die (KGD) screening guarantees pre-assembly functional correctness, yet it offers no probabilistic assurance of post-assembly reliability lifetime. To address this limitation, the present work formalizes the transition from KGD to Known Good Reliable Die (KGRD) screening as a constrained inference problem over incomplete pre-assembly observability. Building upon this formulation, four interlocking contributions are presented: (i) a Bayesian probabilistic risk model that maps pre-assembly telemetry to post-assembly failure likelihood with a quantified observability bias bound; (i) a safety-gated decision architecture that provides a provable post-assembly failure probability guarantee; (i) uncertainty-aware disposition boundaries derived from Bayes-optimal decision theory; and (iv) a constrained closed-loop feedback mechanism that delivers consistent model improvement without violating reliability constraints. A Monte Carlo simulation study on N=4,000N=4,000 synthetic dies verifies all four theoretical properties and confirms that the safety guarantee holds uniformly across the full range of tested gate thresholds. I Introduction The semiconductor industry’s transition toward heterogeneous integration assembling multiple dies, each optimized for a distinct function, into a single advanced package has fundamentally altered the economics and complexity of system-level reliability [1, 2, 3, 4, 5]. Chiplet-based AI SoCs aggregate logic dies, memory dies, and I/O bridge tiles in 2.5D and 3D configurations that place extreme demands on inter-die interconnect integrity [6, 7, 8]. A single reliability failure at the package level can render an entire multi-thousand-dollar assembly unrecoverable, making the cost of post-assembly failure disproportionately high compared to pre-assembly die cost [9]. Conventional Known Good Die (KGD) screening, first formalized in the early 1990s [1, 2], addresses pre-assembly functional correctness: a die that passes structural test, IDDQ screening, and at-speed delay tests is declared “known good” and approved for assembly. The KGD paradigm was well-suited to the package-on-board era, where inter-die interconnects were relatively tolerant of die-level variation. However, heterogeneous chiplet integration introduces qualitatively new failure modes that KGD screening is not designed to detect. Specifically, a die that passes all pre-assembly electrical tests may still fail post-integration due to package-induced mechanical stress [10], thermal gradient mismatch across the die-to-die interconnect layer [11], micro-bump fatigue under cyclic loading [12], or underfill delamination driven by coefficient of thermal expansion mismatch [13]. The defining property of these failure mechanisms is that they are observability-bounded: they depend on package context information substrate material, bump pitch, molding compound properties, and operating thermal profile that is unavailable at the pre-assembly test stage. This observability boundary motivates the concept of Known Good Reliable Die (KGRD) screening, which shifts the objective from immediate pre-assembly pass/fail correctness to predicted post-assembly reliability over the required mission lifetime [14, 15]. KGRD screening must therefore answer a fundamentally harder question than KGD: not “does this die work now?” but “will this die survive the stresses of integration and field operation?” Answering this question from incomplete pre-assembly evidence is, at its core, a constrained statistical inference problem one that has not previously been formalized in the semiconductor test literature. This paper provides that formalization. Section I formalizes the observable feature space and derives a Bayesian probabilistic risk model with a quantified observability bias bound. Section I introduces the safety-gated decision framework and proves the central reliability guarantee. Section IV derives uncertainty-aware disposition rules from Bayes-optimal decision theory. Section V formalizes the constrained closed-loop feedback mechanism and establishes convergence guarantees. Section VI presents a Monte Carlo simulation study. Sections VII and VIII discuss limitations and conclude. I Probabilistic Risk Model I-A Observable Feature Space and the Observability Gap Modern chiplet die screening generates measurements across four physical domains electrical, thermal, structural, and test-signature each carrying partial information about post-assembly reliability [16, 17]. The critical insight is that none of these domains alone, and no feasible combination of them, provides complete information about the failure mechanisms activated by the package integration process itself [10, 13]. We formalize this limitation through the concept of the observability gap. Definition 1 (Observable Feature Space). Let Ω denote the complete space of pre-assembly die observables. The observable feature space is =e×t×s×τ⊂ΩX=X_e×X_t×X_s×X_τ⊂ (1) where eX_e collects electrical signatures (leakage, VthV_th, IDSATI_DSAT); tX_t thermal signatures (junction temperature, thermal resistance); sX_s structural signatures (bump coplanarity, die bow, warpage); and τX_τ test signatures (IDDQ, delay histogram, scan coverage). A die d is represented by x=(xe,xt,xs,xτ)∈x=(x_e,x_t,x_s,x_τ) . The observability gap is Δ=Ω∖≠∅ = ≠ , encoding all failure-relevant information not measurable before integration. Definition 1 captures the essential asymmetry of the KGRD problem: the test engineer observes x∈x , yet must make reliability predictions that depend on the full pre-assembly state Ωd _d as well as the post-assembly package context c∈c . The gap Δ represents structurally inaccessible information, such as the in-situ residual stress distribution in the assembled package or the final thermal interface resistance after underfill cure [10, 12]. This inaccessibility distinguishes KGRD screening from conventional test coverage optimization [18]. I-B Latent Reliability Variable and Failure Indicator Definition 2 (Latent Reliability Variable). Let Td∈ℝ+T_d _+ denote the latent time-to-failure of die d under nominal package operating conditions. TdT_d is unobservable pre-assembly. The reliability failure indicator is Yd=[Td<τmission]Y_d=1[T_d< _mission] (2) where τmission _mission is the required mission lifetime. Yd=1Y_d=1 denotes post-assembly early failure; Yd=0Y_d=0 denotes survival. The binary formulation of Definition 2 is a deliberate modeling choice. Rather than estimating the full distribution of TdT_d, which would require parametric assumptions difficult to validate pre-assembly [19], we target the probability of the reliability event directly. This connects KGRD screening to the literature on binary classification under covariate shift, while preserving the engineering interpretation of a mission-lifetime reliability SLA. I-C Bayesian Posterior Risk Model Definition 3 (Probabilistic Risk Model). Let θ∈Θθ∈ be the model parameter vector with prior p(θ)p(θ), and let Dtrain=(xi,ci,yi)i=1ND_train=\(x_i,c_i,y_i)\_i=1^N be historical post-assembly outcome data. The risk model is the posterior predictive R(x,c)=∫ΘP(Yd=1∣x,c,θ)p(θ∣Dtrain)θR(x,c)= _ P(Y_d=1 x,c,θ)\,p(θ D_train)\,dθ (3) with logistic parametric likelihood P(Yd=1∣x,c,θ)=σ(θTϕ(x,c))P(Y_d=1 x,c,θ)=σ(θ^Tφ(x,c)), where σ(⋅)σ(·) is the logistic sigmoid and ϕ:×→ℝpφ:X×C ^p is a feature map. Predictive uncertainty is quantified by the posterior predictive variance U(x,c)U(x,c). The logistic likelihood is log-concave in θ, guaranteeing a unique MAP estimate and making the constrained optimization of Section V tractable [20]. The posterior predictive variance U(x,c)U(x,c) plays a dual role: it enters the safety gate as a conservatism buffer in Section I, and drives the retest disposition decision when uncertainty is high in Section IV [21]. Machine learning methods have recently been applied broadly to semiconductor process optimization and yield prediction [22, 23, 24]; the KGRD framework differs in targeting post-assembly reliability rather than pre-assembly yield, and in providing formal safety guarantees absent from those approaches. I-D Observability Bias Bound Proposition 1 (Observability Bias Bound). For any die d with observation x∈x and context c∈c , let R^(x,c) R(x,c) be the risk estimated from observed features and RtrueR_true be the oracle risk. Then |R^(x,c)−Rtrue|≤εΔ(x,c)| R(x,c)-R_true|≤ _ (x,c) (4) where εΔ(x,c)=supω∈Δ|∂P(Yd=1)/∂ω|⋅‖ω‖ _ (x,c)= _ω∈ |∂ P(Y_d=1)/∂ω|·\|ω\| is the maximum first-order sensitivity of failure probability to unobserved features, estimated from held-out validation data. Proof sketch: The bound follows from a first-order Taylor expansion of P(Yd=1∣Ωd,c)P(Y_d=1 _d,c) around x. The supremum over Δ gives the worst-case deviation. Consistency as N→∞N→∞ follows from standard empirical process theory under sub-Gaussian tail assumptions on ϕφ. □ The bias bound εΔ _ cannot be reduced by improving observable test coverage alone. It can only be reduced by (i) moving previously unobserved features from Δ into X through new measurement capabilities, or (i) accumulating post-assembly failure observations that implicitly calibrate the model against package-induced effects. The latter pathway directly motivates the closed-loop feedback mechanism of Section V [25]. I Safety-Gated Decision Framework I-A The Prediction-Authorization Separation Principle A fundamental pitfall in deploying machine learning models for high-stakes manufacturing decisions is what we term prediction-authorization conflation: allowing a statistical model’s output to directly authorize a release decision without an independent deterministic check. In the KGRD context, such conflation is particularly dangerous because the risk model of Definition 3 is, by Proposition 1, unavoidably biased in the presence of the observability gap. The safety-gated architecture prevents this by separating statistical estimation from deterministic authorization through an independent gate function that cannot be overridden by the model, consistent with broader safety-critical system design philosophy. I-B Safety Gate Definition Definition 4 (Safety Gate). A safety gate G:×ℝ×ℝ+→PASS,BLOCKG:X×C×R×R_+→\PASS,BLOCK\ is defined by G=PASSif R+kU≤αrel and H=TRUEBLOCKotherwiseG= casesPASS&if R+k U≤ _rel and H=TRUE\\[2.0pt] BLOCK&otherwise cases (5) where k≥0k≥ 0 is the uncertainty inflation factor (k=1.645k=1.645 enforces a 95th-percentile bound), αrel∈(0,1) _rel∈(0,1) is the maximum permissible failure probability (the reliability SLA), and H(x,c)H(x,c) is a vector of hard deterministic guard conditions. The uncertainty inflation term kU(x,c)k U(x,c) implements a conservative risk estimate that accounts for model uncertainty without requiring the model to be perfectly calibrated [21, 20]. The hard constraint set H(x,c)H(x,c) provides a deterministic backstop for failure modes the probabilistic model may not capture. I-C Central Reliability Guarantee Theorem 1 (Safety Gate Reliability Guarantee). Let Drel=d:G(xd,cd,Rd,Ud)=PASSD_rel=\d:G(x_d,c_d,R_d,U_d)=PASS\. Under the conditions (A1) R(x,c)+εΔ(x,c)≥RtrueR(x,c)+ _ (x,c)≥ R_true almost surely; (A2) U(x,c)≥Var[Rtrue∣x,c]U(x,c) [R_true x,c] almost surely; (A3) H(x,c)=TRUEH(x,c)=TRUE is necessary for post-assembly reliability; for every released die d∈Dreld∈ D_rel: P(Yd=1)≤αrel+εΔ(xd,cd).P(Y_d=1)≤ _rel+ _ (x_d,c_d). (6) Proof sketch: For any d∈Dreld∈ D_rel, the gate condition implies R(xd,cd)+kU(xd,cd)≤αrelR(x_d,c_d)+k U(x_d,c_d)≤ _rel. By (A2), kU≥0k U≥ 0, hence R(xd,cd)≤αrelR(x_d,c_d)≤ _rel. By (A1), P(Yd=1)=Rtrue≤R(xd,cd)+εΔ≤αrel+εΔP(Y_d=1)=R_true≤ R(x_d,c_d)+ _ ≤ _rel+ _ . The bias correction vanishes as Δ→∅ → ; condition (A3) ensures gross structural failures excluded by H do not violate the bound. □ Theorem 1 has a direct engineering consequence for SLA setting: αrel _rel should be set as αtarget−εΔ _target- _ , tighter than the actual target by exactly the observability bias, so that the true post-assembly failure rate remains within the target budget even in the presence of the measurement gap. IV Uncertainty-Aware Disposition Rules IV-A Five-Region Disposition Map Theorem 1 establishes the binary boundary between releasable and non-releasable dies. In practice, the space of non-releasable dies is not homogeneous: a die with high risk and low uncertainty should be treated differently from a die with moderate risk and high uncertainty, or a die with low risk blocked only because model uncertainty is too high. Collapsing all three into a single “BLOCK” outcome wastes economically recoverable dies and destroys diagnostic information [26]. Definition 5 (Five-Region Disposition Map). Let r=R(x,c)+kU(x,c)r=R(x,c)+k U(x,c) be the uncertainty-inflated risk score and u=U(x,c)u= U(x,c) the raw predictive uncertainty. For thresholds 0<αr<αst<αbg≤10< _r< _st< _bg≤ 1 and u∗>0u^*>0: DRD_R: r≤αr∧u≤u∗r≤ _r u≤ u^* → RELEASE DRTD_RT: r≤αr∧u>u∗r≤ _r u>u^* → RETEST DSSD_S: αr<r≤αst∧u≤u∗ _r<r≤ _st u≤ u^* → STRESS-SCREEN DBGD_BG: αst<r≤αbg _st<r≤ _bg → LOWER-GRADE BIN DREJD_REJ: r>αbgr> _bg → REJECT The RETEST region DRTD_RT captures dies whose inflated risk is acceptably low but whose uncertainty u>u∗u>u^* indicates the model lacks sufficient confidence to release the die without additional evidence. The STRESS-SCREEN region DSSD_S captures dies that are too risky for direct release but whose risk level is consistent with post-burn-in survival [27], providing a recovery path for economically valuable dies. IV-B Bayes-Optimal Threshold Derivation The disposition thresholds are derived from Bayes-optimal decision making under asymmetric cost [28, 29]. Table I defines the cost structure. The asymmetry CFR≫CFRJC_FR C_FRJ is a consequence of chiplet assembly economics: a false release wastes the entire package, while a false rejection wastes only the die [9, 30]. TABLE I: Screening Cost Structure Cost Symbol Interpretation False release CFRC_FR Package loss + rework False reject CFRJC_FRJ Yield loss from rejection Stress screen CSSC_S Incremental burn-in cost Lower-grade bin CBGC_BG Downgrade revenue loss Theorem 2 (Bayes-Optimal Release Threshold). Under an asymmetric cost structure with CFR≫CFRJC_FR C_FRJ, the release threshold minimizing expected total screening cost is αr∗=CFRJCFR+CFRJ. _r^*= C_FRJC_FR+C_FRJ. (7) For the general five-region case, the Bayes-optimal disposition minimizes the expected loss subject to the safety gate constraint, which is never relaxed by cost optimization. Proof sketch: For the binary case, the expected loss for RELEASE is CFR⋅rC_FR· r and for REJECT is CFRJ(1−r)C_FRJ(1-r). Setting these equal gives αr∗=CFRJ/(CFR+CFRJ) _r^*=C_FRJ/(C_FR+C_FRJ). Extension to five regions solves three sequential threshold comparisons. The safety gate constraint enters by removing the RELEASE option when G=BLOCKG=BLOCK regardless of cost, which can only increase expected loss; hence the constraint cannot be relaxed by the optimizer. □ IV-C Retest Value of Information Proposition 2 (Retest Value of Information). The value of an additional measurement x′x is VoI(x) (x) =CFR⋅r⋅Prej(x′) =C_FR· r· P_rej(x ) +CFRJ(1−r)Prel(x′)−Cretest +C_FRJ(1-r)\,P_rel(x )-C_retest (8) where Prej(x′)P_rej(x ) and Prel(x′)P_rel(x ) denote the reclassification probabilities to DREJD_REJ and DRD_R. Retest is warranted iff VoI(x)>0VoI(x)>0. Dies near the DR/DRTD_R/D_RT boundary have the highest expected reclassification probability and therefore the highest VoI, consistent with the active-learning finding that uncertainty-sampled examples yield the most decision-relevant information [31]. V Constrained Closed-Loop Feedback V-A Post-Assembly Observation and Survivorship Bias The risk model of Definition 3 is trained on historical post-assembly outcome data DtrainD_train. As new chiplet assemblies are released and operated, post-assembly failure observations become available to update the model [32, 33]. However, a critical statistical complication arises: the feedback observations are a selected sample specifically, the subset of dies approved by the safety gate of Definition 4. Dies in regions DRT,DSS,DBGD_RT,D_S,D_BG, and DREJD_REJ are not assembled and therefore do not contribute post-assembly outcomes. This is a classic survivorship bias problem [34], which, if uncorrected, will bias the updated model toward optimism. Definition 6 (Feedback Observation Set). After assembly and early-life operation, the feedback corpus at iteration t is Ot=(xd,cd,yd):d∈Drel,Td<τobsO_t=\(x_d,c_d,y_d):d∈ D_rel,\,T_d< _obs\ (9) where τobs≤τmission _obs≤ _mission is the observation horizon. Only released dies contribute to OtO_t, creating the survivorship selection bias. V-B Constrained Model Update Rule Theorem 3 (Constrained Model Update Rule). The constrained MAP update at iteration t is θt+1=argmaxθ∈Θsafe[ℓcorr(θ;Ot)+logp(θ∣θt)] _t+1= _θ∈ _safe [ _corr(θ;O_t)+ p(θ _t) ] (10) where the survivorship-corrected log-likelihood is ℓcorr(θ)=∑(x,c,y)∈Otw(x,c)logPθ(Y=y∣x,c) _corr(θ)= _(x,c,y)∈ O_tw(x,c)\, P_θ(Y=y x,c) (11) and the safety feasibility set is Θsafe=θ∈Θ:∀(x,c), _safe= \θ∈ :∀(x,c),\; Pθ(Y=1∣x,c) P_θ(Y=1 x,c) +kVarθ[Y∣x,c] +k Var_θ[Y x,c] ≤αrel+εΔ. ≤ _rel+ _ \. (12) The Θsafe _safe constraint ensures θt+1 _t+1 satisfies Theorem 1 for all future decisions. Proof sketch: The constrained problem is well-posed: the log-posterior is strictly concave in θ, and Θsafe _safe is a convex set. Existence and uniqueness follow from strong duality of the constrained concave maximization. □ V-C Survivorship Bias Correction Proposition 3 (Survivorship-Corrected Likelihood). The selection-corrected log-likelihood uses importance weight w(x,c)=1P(G(x,c,Rθ,Uθ)=PASS).w(x,c)= 1P(G(x,c,R_θ,U_θ)=PASS). (13) As αrel→1 _rel→ 1, w(x,c)→1w(x,c)→ 1 (no correction needed). As αrel→0 _rel→ 0, w(x,c)→∞w(x,c)→∞ (each survivor is highly informative). Proof sketch: By Bayes’ rule, and because the gate decision depends on (x,c)(x,c) but not on Y, the conditional likelihood ratio reduces to 1/P(selected∣x,c)1/P(selected x,c). □ V-D Convergence Guarantees Theorem 4 (Feedback Loop Convergence). Under the constrained update rule of Theorem 3, the sequence θtt≥0\ _t\_t≥ 0 satisfies: (C1) Safety invariance: θt∈Θsafe _t∈ _safe for all t≥0t≥ 0; (C2) Monotone uncertainty: Uθt≥Uθt+1U_ _t≥ U_ _t+1 a.s. as |Ot|→∞|O_t|→∞; (C3) Asymptotic consistency: θt→θtrue _t→ _true in probability if θtrue∈Θsafe _true∈ _safe. Proof sketch: (C1) holds by construction since Θsafe _safe is enforced as a hard constraint at every iteration. (C2) follows from Fisher information monotonicity of the Bayesian posterior. (C3) is a standard consequence of constrained MAP consistency [33]. □ Theorem 4 has a critical practical implication: property (C1) holds even if θtrue _true lies near or on the boundary of Θsafe _safe. An unconstrained online learner might oscillate across the boundary, producing iterations in which the reliability guarantee is violated. Property (C2) provides the formal basis for the intuition that screening improves as post-assembly data accumulates: the conservative uncertainty buffer in the gate shrinks monotonically, allowing an increasing fraction of reliable dies to be released over time. VI Monte Carlo Simulation Study VI-A Experimental Setup To verify the four theoretical properties under controlled synthetic conditions, we conduct a Monte Carlo simulation study [26, 35]. Feature distributions are calibrated to open-literature chiplet process characterization data [16, 36, 37]. Bump coplanarity deviation follows Clip((0,2.0),−5,5)μmClip(N(0,2.0),-5,5)\, ; thermal resistance deviation follows Clip((0,1.5),−4,4)Clip(N(0,1.5),-4,4) K/W; log-leakage follows (0,1.0)N(0,1.0); IDDQ anomaly score follows (0,0.8)N(0,0.8); die bow follows |(0,2.5)|μm|N(0,2.5)|\, ; and scan delay skew follows (0,0.6)N(0,0.6). The true parameter vector is θtrue=[−1.8,0.50,0.42,0.18,0.14,0.22,0.09]T _true=[-1.8,0.50,0.42,0.18,0.14,0.22,0.09]^T, yielding a base post-assembly failure rate of approximately 14%, consistent with reported early-life failure rates in advanced chiplet packaging before reliability screening [38]. VI-B Risk Model Validation The fitted logistic model achieves good calibration against the oracle risk for N=500N=500 test dies. To introduce the observability gap, structural and test-signature features (die bow and scan delay) are set to zero, simulating a scenario in which these measurements were not taken pre-assembly [17]. A systematic upward and downward bias becomes visible. From the resulting bias distribution, the 95th-percentile observability bound is estimated as εΔ=0.133 _ =0.133, used in all subsequent safety gate computations. VI-C Safety Gate Guarantee Verification Gate thresholds αrel∈[0.10,0.80] _rel∈[0.10,0.80] are swept across N=3,000N=3,000 evaluation dies. The observed post-assembly failure rate of released dies lies strictly below the theoretical bound αrel+εΔ _rel+ _ at every tested threshold, confirming that Theorem 1’s guarantee is numerically tight. Tightening αrel _rel from 0.800.80 to 0.100.10 reduces the release rate from near 100% to approximately 5%. VI-D Disposition Region Verification The five-region disposition map for N=800N=800 evaluation dies is plotted in the risk-uncertainty plane. With CFR=10C_FR=10 and CFRJ=2C_FRJ=2, Theorem 2 gives αr∗=0.167 _r^*=0.167. At this conservative threshold, the majority of dies fall into the stress-screen, lower-grade bin, or reject regions [30]. Plotting αr∗ _r^* against the cost ratio CFR/CFRJC_FR/C_FRJ confirms that tighter thresholds are required as the relative cost of false release grows. VI-E Feedback Loop Convergence Starting from a deliberately misspecified prior dominant feature weights reduced to 25% of their true values and the intercept lowered by 0.80.8 the constrained MAP update of Theorem 3 is applied for T=20T=20 iterations with 200 cumulative dies per iteration [39, 40]. Parameter error ‖θt−θtrue‖2\| _t- _true\|_2 decreases from 1.351.35 to 0.780.78 (42% reduction), confirming (C3). The safety-compliant fraction remains above 98% at every iteration, confirming (C1). Mean model uncertainty decreases monotonically, confirming (C2). VI-F Summary TABLE I: Simulation Study Summary Property Result Status Calibration (Def. 3) εΔ=0.133 _ =0.133 ✓ Bias bound (Prop. 1) Bias ≤εΔ≤ _ at 95% ✓ Safety gate (Thm. 1) Fail rate <αrel+εΔ< _rel+ _ ✓ Optimal threshold (Thm. 2) αr∗=0.167 _r^*=0.167 ✓ Convergence (Thm. 4) C1, C2, C3 satisfied ✓ VII Discussion and Limitations VII-A Scope of Validation The simulation study verifies internal consistency of the theoretical framework, but real-world deployment will require validation against actual chiplet process data across multiple foundries and packaging technologies [35]. The bounds and constants derived here provide quantitative design targets to guide that experimental effort. A companion paper reporting experimental results on real ATE/PTE fab data is planned as the next phase of this work. VII-B Model Expressivity The logistic model is chosen for its tractability and interpretability. Gaussian process classifiers provide a natural Bayesian uncertainty quantification framework with closed-form posterior updates [21], and deep neural feature maps can capture nonlinear interactions that a linear logistic model misses [25]. Any substitute model must produce a calibrated uncertainty estimate satisfying condition (A2) of Theorem 1, and have a log-concave likelihood to ensure the constrained update of Theorem 3 is tractable [20]. VII-C Non-Stationary Context and Multi-Die Dependencies The framework treats the package context vector c as fixed and fully known. In production, c may be partially uncertain, introducing a second layer of observability gap beyond Δ . Furthermore, the KGRD framework currently treats dies independently. In 2.5D and 3D packages, the thermal and mechanical state of one die influences the reliability of its neighbors through substrate bending and heat spreading [7, 11], introducing conditional dependence that requires a joint risk model over die tuples [41]. VII-D Active Screening Design Proposition 2’s Value of Information framework opens a path toward active screening design: rather than applying a fixed test sequence to all dies, the framework can prioritize additional tests based on their expected VoI [31]. This connects KGRD screening to the broader literature on Bayesian experimental design, and suggests a formulation of joint test content selection and reliability disposition as a single optimization problem. VIII Conclusion This paper has established the first formally grounded treatment of Known Good Reliable Die screening for chiplet-based AI SoCs [1, 2]. Beginning from the observation that conventional KGD screening addresses correctness but not reliability, we formalized die screening as a constrained inference problem over an observability-bounded pre-assembly measurement space. Four interlocking contributions emerged: a Bayesian posterior risk model with a quantified observability bias bound, a safety-gated architecture with a provable post-assembly failure probability guarantee, Bayes-optimal disposition thresholds derived from asymmetric misclassification cost, and a constrained closed-loop feedback rule that achieves safety invariance, monotone uncertainty reduction, and asymptotic consistency simultaneously. A Monte Carlo simulation study on N=4,000N=4,000 synthetic dies confirmed all theoretical properties and demonstrated that the safety guarantee holds uniformly across the full range of gate thresholds tested. The theoretical separation between statistical estimation and deterministic release authorization ensures that no predictive model can unilaterally approve a die for integration into a high-value chiplet assembly. The safety gate converts unavoidable model uncertainty into a conservative safety margin formally bounded by Proposition 1 and Theorem 1 working in concert. The present work is intended as the first in a two-part series. This paper establishes the formal theoretical foundation the definitions, theorems, proofs, and synthetic verification that makes KGRD screening a mathematically rigorous discipline. A follow-on paper is planned to report experimental validation of the complete framework on real ATE/PTE data from production-grade 2.5D AI chiplet assemblies, including empirical estimation of εΔ _ from field return analysis, safety gate calibration against actual post-assembly burn-in outcomes, and closed-loop feedback convergence measured over multiple production lots. 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