Paper deep dive
CORVET: A CORDIC-Powered, Resource-Frugal Mixed-Precision Vector Processing Engine for High-Throughput AIoT applications
Sonu Kumar, Mohd Faisal Khan, Mukul Lokhande, Santosh Kumar Vishvakarma
Intelligence
Status: succeeded | Model: Gemma-4-26B-A4B | Prompt: intel-v1 | Confidence: 91%
Last extracted: 7/20/2026, 8:17:33 PM
Summary
The paper introduces CORVET, a runtime-adaptive, resource-efficient vector processing engine for edge AI applications. It utilizes an iterative CORDIC-based Multiply-Accumulate (MAC) unit that allows dynamic reconfiguration between approximate and accurate modes to optimize the latency-accuracy trade-off. The architecture features a time-multiplexed multi-activation function (multi-AF) block and supports flexible precision (4/8/16-bit). Implemented in 28 nm ASIC, the 256-PE configuration achieves 4.83 TOPS/mm² compute density and 11.67 TOPS/W energy efficiency, outperforming state-of-the-art designs.
Entities (10)
Relation Signals (8)
CORVET → achieves → 4.83 TOPS/mm2
confidence 95% · with a 256-PE configuration that achieves higher compute density (4.83 TOPS/mm2 )
CORVET → achieves → 11.67 TOPS/W
confidence 95% · and energy efficiency (11.67 TOPS/W) than previous state-of-the-art work.
CORVET → uses → CORDIC
confidence 95% · The proposed design enables dynamic reconfiguration between approximate and accurate modes... featuring a low-resource, iterative CORDIC-based MAC unit
CORVET → implements → MAC Unit
confidence 92% · This brief presents a runtime-adaptive, performance-enhanced vector engine featuring a low-resource, iterative CORDIC-based MAC unit
CORVET → supports → multi-AF Block
confidence 90% · With a time-multiplexed multi-AF block... the proposed vector engine supports flexible precision
CORVET → evaluatedon → Pynq-Z2
confidence 88% · A detailed hardware-software co-design methodology for object detection and classification tasks on Pynq-Z2 is discussed
multi-AF Block → supports → Sigmoid
confidence 85% · The multi-AF block supports a broad set of nonlinear functions, including Sigmoid
multi-AF Block → supports → ReLU
confidence 85% · The multi-AF block supports a broad set of nonlinear functions, including ... ReLU
Cypher Suggestions (0)
No Cypher suggestions yet.
Abstract
Abstract:This brief presents a runtime-adaptive, performance-enhanced vector engine featuring a low-resource, iterative CORDIC-based MAC unit for edge AI acceleration. The proposed design enables dynamic reconfiguration between approximate and accurate modes, exploiting the latency-accuracy trade-off for a wide range of workloads. Its resource-efficient approach further enables up to 4x throughput improvement within the same hardware resources by leveraging vectorised, time-multiplexed execution and flexible precision scaling. With a time-multiplexed multi-AF block and a lightweight pooling and normalisation unit, the proposed vector engine supports flexible precision (4/8/16-bit) and high MAC density. The ASIC implementation results show that each MAC stage can save up to 33% of time and 21% of power, with a 256-PE configuration that achieves higher compute density (4.83 TOPS/mm2 ) and energy efficiency (11.67 TOPS/W) than previous state-of-the-art work. A detailed hardware-software co-design methodology for object detection and classification tasks on Pynq-Z2 is discussed to assess the proposed architecture, demonstrating a scalable, energy-efficient solution for edge AI applications.
Tags
Links
- Source: https://arxiv.org/abs/2602.19268v1
- Canonical: https://arxiv.org/abs/2602.19268v1
Trouble viewing inline? Open PDF directly →
Full Text
56,180 characters extracted from source content.
Expand or collapse full text
1 CORVET: A CORDIC-Powered, Resource-Frugal Mixed-Precision Vector Processing Engine for High-Throughput AIoT applications Sonu Kumar , Mohd Faisal Khan, Mukul Lokhande, Member, IEEE, and Santosh Kumar Vishvakarma , Senior Member, IEEE Abstract—Thisbriefpresentsaruntime-adaptive, performance-enhanced vector engine featuring a low-resource, iterative CORDIC-based MAC unit for edge AI acceleration. The proposed design enables dynamic reconfiguration between approximate and accurate modes, exploiting the latency-accuracy trade-off for a wide range of workloads. Its resource-efficient approach further enables up to 4× throughput improvement within the same hardware resources by leveraging vectorised, time-multiplexed execution and flexible precision scaling. With a time-multiplexed multi-AF block and a lightweight pooling and normalisation unit, the proposed vector engine supports flexible precision (4/8/16-bit) and high MAC density. The ASIC implementation results show that each MAC stage can save up to 33% of time and 21% of power, with a 256-PE configuration that achieves higher compute density (4.83 TOPS/m 2 ) and energy efficiency (11.67 TOPS/W) than previous state-of-the-art work. A detailed hardware-software co-design methodology for object detection and classification tasks on Pynq-Z2 is discussed to assess the proposed architecture, demonstrating a scalable, energy-efficient solution for edge AI applications. Index Terms—CORDIC, multiply-accumulate (MAC), Non- linear Activation Functions, deep learning accelerators, Internet of things, Reconfigurable Computing. I. INTRODUCTION D EEP learning has become a foundational component of modern artificial intelligence (AI) systems at the Internet of things (IoT), enabling breakthroughs across com- puter vision, speech recognition, natural language processing, and autonomous systems. Contemporary workloads are domi- nated by Deep Neural Networks (DNNs), Vision Transformers (ViTs), and emerging large-scale models, whose inference and training pipelines are primarily composed of convolutional layers, fully connected (FC) or multi-layer perceptron (MLP) blocks, and attention mechanisms [1]–[6]. Despite architec- tural diversity, workload characterisation studies consistently show that multiply-accumulate (MAC) operations account for approximately 90% of total computation, while non-linear acti- vation functions (NAFs) contribute an additional 2-5% [3], [5]. Efficient execution of these operations is therefore critical for deploying AI models on resource-constrained edge platforms [7], [8]. To address the stringent energy, area, and latency constraints of edge AI, prior work has explored several hardware optimi- sation techniques, including fixed-point quantization [3], [9], Sonu Kumar, Mohd Faisal Khan and Santosh Kumar Vishvakarma acknowl- edge DST INSPIRE fellowship and MeitY/SMDP-C2S for ASIC tool support. Sonu Kumar is with the Centre for Advanced Electronics, IIT Indore. Mohd Faisal Khan, Mukul Lokhande, and Santosh Kumar Vishvakarma are with the NSDCS Research Group, Dept. of Electrical Engineering at IIT Indore. Corresponding author: Santosh K. Vishvakarma (skvishvakarma@iiti.ac.in). CORDIC-based arithmetic [5], logarithmic approximation [4], [10], and truncation-based MAC units [2], [11]. While these approaches achieve notable reductions in computational com- plexity and power consumption, they typically operate at a fixed approximation point. As a result, either irreversible accu- racy degradation is incurred, or additional error-compensation mechanisms are required, which partially negate the energy benefits [2], [3]. Furthermore, these designs often lack the flexibility to dynamically adjust approximation depth based on layer sensitivity or application requirements [12], [13]. Recent edge-oriented deep learning accelerators focus on energy efficiency, reduced memory traffic, and architectural flexibility by leveraging efficient dataflows, reconfigurable systolic arrays, and pipeline-aware designs. Complementary approaches exploit computing-in-memory, quantised and bi- nary neural networks, and tightly integrated SoC platforms to alleviate bandwidth and storage bottlenecks requirements [14], [15] [16]. In parallel, recent studies have highlighted a struc- tural inefficiency in many deep learning accelerators: the dis- proportionate allocation of hardware resources to activation- function units. Although AFs constitute a small fraction of total operations, they are frequently implemented using dedi- cated hardware blocks that remain idle for a significant portion of execution. Prior work reports up to 84% idle cycles in NAF hardware for layer-reused architectures [11], while large- scale commercial accelerators such as Google TPUv4 allocate nearly 20–25% of chip area to activation-related logic [3]. This imbalance results in substantial dark silicon, limiting overall energy efficiency and scalability. Table I provides a comparative overview of state-of-the-art (SoTA) AI accelerator designs, highlighting key architectural choices, supported precision, scalability, and associated trade- offs. Existing CORDIC- and approximation-based designs pre- dominantly employ pipelined or fixed-stage implementations, which constrain runtime flexibility and enforce static accuracy- latency operating points [17]–[21]. In contrast, recent layer- reused or time-multiplexed architectures improve utilization but still lack fine-grained control over numerical accuracy at the MAC level. Consequently, prior designs are not very flexible with respect to different layer characteristics and operating conditions. They often require predefined datapaths and static precision settings [22], [23]. This rigidity leads to suboptimal trade-offs among accuracy, latency, and resource utilisation when deployed across heterogeneous deep learning workloads [24], particularly for models that demand mixed- precision computation and flexible activation support. This paper addresses these limitations by proposing a runtime-adaptive, CORDIC-accelerated vector engine that ex- arXiv:2602.19268v1 [cs.AR] 22 Feb 2026 2 TABLE I SOTA DESIGN APPROACHES AND COMPARISON OF RESPECTIVE DESIGN FEATURES IN AI WORKLOADS DesignBaselineICIIS’25 [11]ICIIS’25 [11]IEEE Access’24 [2]TVLSI’25 [3]ISCAS’25 [4]ISVLSI’25 [5]Proposed ComputePipe-CORDICPipe-CORDICPWLPipe-CORDICPipe-CORDICLogarithmic Approx.Iterative CORDICIterative CORDIC Arch. TypeFully ParallelLayer-ReusedNAF-ReusedNAF-ReusedSystolic Array Time-multiplexed Reconfigurable Array Layer-ReusedVector Engine ScalabilityNoYesNoNo-YesNoYes PrecisionFxP-8FxP-8FxP-8FxP-8FxP-4/8/16/32Posit-8/16/32FxP-8FxP-4/8/16 Accuracy lossHighHighHighHighMediumLowMediumVariable (Low) Design OverheadArea, St. PowerAreaArea, St. PowerArea, PowerEnergyArea, ComplexityLatency Application-optimized High-Throughput NAF-SupportedReLUReLUSigmoid/TanhNA Sigmoid, Softmax, Tanh, ReLU Sigmoid, Tanh, Softmax Sigmoid/Tanh SoftMax, GELU, Sigmoid Tanh, Swish, ReLU, and SELU ApplicationsANNANNANNDNNDNN, TransformersDNNDNNDNN, Transformers (MLP) plicitly exposes MAC precision, approximation depth, and execution latency as configurable architectural parameters. Unlike prior fixed-approximation designs, the proposed ap- proach enables seamless switching between approximate and accurate execution modes without structural modification or auxiliary correction logic. In addition, a time-multiplexed multi-activation-function (multi-NAF) block is integrated to maximise hardware utilisation and significantly reduce dark silicon. The key contributions of this work are summarised as follows: 1) A low-resource, iterative CORDIC-based MAC unit with runtime-configurable accuracy-latency trade-offs, sup- porting both approximate and accurate execution modes. 2) A scalable vector-engine architecture that amortises iter- ative MAC latency across parallel lanes, enabling higher throughput 4× without excessive area overhead. 3) A high-utilisation, time-multiplexed multi-NAF block supporting a wide range of nonlinear functions with minimal additional hardware cost. 4) A comprehensive evaluation spanning software emula- tion, FPGA prototyping, and 28 nm ASIC synthesis, demonstrating system-level improvements on CNN and transformer-style workloads. The remainder of this paper is organised as follows. Sec- tion I presents the proposed vector-engine architecture. Sec- tion I details the circuit-level implementation of the iterative MAC and multi-NAF blocks. Section IV describes the ex- perimental methodology and evaluation framework. Section V discusses FPGA, ASIC, and system-level results. Section VI concludes the paper and outlines future research directions. I. ARCHITECTURE OVERVIEW Fig. 1 illustrates the top-level architecture of the proposed resource-efficient deep learning accelerator. The system is organised around a runtime-adaptive vector engine that serves as the primary compute core, supported by a lightweight con- trol engine, data prefetcher, time-multiplexed multi-activation- function (multi-AF) block, pooling and normalisation units, and off-chip memory interfaces. The architecture is designed to maximise compute utilisation while enabling flexible trade- offs between accuracy and latency across diverse deep learning workloads. Input Feature Map Data- Address Manager Input Tracker Configurable MULTI-AF Block, AAD Pooling, Norm/Encoding Unit External Off-Chip Memory (featuremaps, kernels) Parameters Allocator Control Engine Kernel Memory Bank #0 Kernel Memory Bank #1 Kernel Memory Bank #n MAC #0 MAC #1 MAC #n Input Data Pre-processor Compute Core Module Lightweight CNN Accelerator Fig. 1. Block-level architecture of the proposed CORDIC-based vector engine integrated within a resource-efficient deep learning accelerator. A. Vector Engine Organization The vector engine is composed of N homogeneous pro- cessing elements (PEs), where N is scalable from 64 to 256 depending on performance and area constraints. Each PE in- tegrates a precision-adjustable, accuracy-configurable iterative CORDIC-based MAC unit, local register storage, and interface logic for data and control synchronisation. Unlike fully parallel systolic arrays, the proposed vector engine adopts a lane-based execution model, amortising the latency of iterative computa- tions across multiple PEs to enable high throughput without requiring deeply pipelined or resource-intensive datapaths. Two dedicated kernel memory banks, each organised as (n-bit ×32) entries, are employed to store input activations and weights, respectively. This dual-bank organisation enables continuous data feeding to the PEs while overlapping memory access with computation. The memory interface is designed to support flexible precision modes (4/8/16-bit) and runtime reconfiguration without stalling the compute pipeline. B. Runtime Accuracy and Precision Adaptation A key architectural feature of the proposed vector engine is its ability to dynamically adapt computation accuracy and latency at runtime. This is achieved by controlling the number 3 Layer Done and ANN Done Assignment Current Layer Assignment Input Muxing Generate Inputs for Neuraons Output Muxing ComputeDone (from Neurons ) Current_Layer LayerDone LayerDone Current_Layer Input Layer Intermediate Input Index Current_Layer Output from Neurons LayerDone Current_Layer Intermediate Input Intermediate Output Intermediate Input to Neurons ComputeInit to Neurons DNNDone Output Intermediate Output Control Modules Sub-blocks for Layer Multiplexed DNN Data Signal: Control Signal: Fig. 2. Control Engine for efficient reuse of data and control signals in a layer-multiplexed for reusing the same DNN architecture. of active CORDIC iterations within each MAC unit on a per- layer basis. Layers that are less sensitive to numerical error can be executed in an approximate mode with fewer iterations, thereby reducing latency and energy consumption. Conversely, accuracy-critical layers operate in a more accurate mode with additional iterations, incurring modest latency overhead while preserving numerical fidelity. This runtime configurability is managed by the control engine through a set of configuration registers that specify precision mode, iteration count, and execution sequencing for each layer. Unlike prior approximation-based accelerators that rely on fixed hardware stages or static design-time tuning [3], [4], the proposed architecture enables fine-grained, layer- wise adaptation without requiring structural modification or auxiliary correction logic. C. Control Engine and Data Flow The control engine orchestrates vector-engine execution by managing instruction sequencing, memory addressing, and synchronisation across PEs. It comprises configuration reg- isters for precision and iteration control, status registers for pipeline coordination, and a finite-state machine with datapath (FSMD) that governs layer execution. This lightweight control logic enables efficient coordination between compute, memory access, and activation processing while minimising control overhead. A layer-multiplexed DNN requires a dedicated control unit composed of five functional sub-blocks, as illustrated in Fig. 2. Each sub-block either monitors system status or produces control signals derived from that status. The control unit processes all status signals: LayerDone, DNNDone, Current- Layer, ComputeInit, Index, and ComputeDone. The neuron processing elements produce Index and ComputeDone, two of the status signals, while the control module internally generates the remaining signals. The Index signal indicates which input to send next to the MAC unit by counting the number of MAC operations completed in the active layer. The ComputeDone signal indicates that neuron computation for the current layer has completed and that valid output data is available. When aggregated across all neuron units, this signal is referred to as ComputeDoneArray. Together, these status signals manage the data-path control necessary for the layer- multiplexed architecture to function properly. The control module dynamically configures neuron activa- tion and signal routing for layer-reused DNN computation. LayerDone and CurrentLayer are used to track progress, Com- puteInit is used to selectively activate neurons per layer, and index-controlled input and output routes are used to multiplex intermediate data. This reduces dynamic power by enabling idle-unit deactivation and ensuring correct sequencing. As the weight memory is partitioned into 64 segments, each associated with a specific neuron processing unit, as depicted in Fig. 3(a). A key aspect of the parameter-loading mechanism is that the memory write sequence is the inverse of the read sequence. This organisation enables efficient access to weights and bias values with reduced interconnect delay. Consequently, parameters must be loaded using a Last-In–First-Out (LIFO) ordering for both weights and biases, as well as for input data. Data transfer follows a synchronous interface using a valid signal, denoted as load_param_weight, to indicate when weight values are written. The accelerator asserts a data- ready signal, DNNDone, once valid outputs are produced. Input values are accepted on each clock cycle when the valid signal is active. Upon completion, outputs from all ten neurons are generated simultaneously when DNNDone is asserted and are subsequently captured by the host software. The overall software-controlled execution sequence of the accelerator is illustrated in Fig. 3(b). Data flow within the accelerator follows a streaming exe- cution model. Input feature maps are fetched from off-chip memory through the data pre-fetcher and buffered locally before being broadcast to the vector engine. Partial sums generated by the PEs are forwarded either to subsequent MAC stages or to the activation function pipeline, depending on the layer configuration. This streaming approach minimises inter- mediate storage requirements and reduces memory bandwidth pressure, both of which are critical for energy-efficient edge deployment. D. Memory mapping The hardware architecture of fully connected neural net- works must support scalable, adaptable setups, as the number of layers and neurons per layer varies across applications. As a result, the memory organisation for weights and biases must be adaptable and avoid allocating unused address locations, a lim- itation commonly encountered in fixed-addressing schemes. This is accomplished by using BRAM for on-chip parameter 4 . . . . . . . . . . . Neuron_63 Neuron_1 Neuron_0 . . . . . . . . Wei ghts [#weight63][8:0] Wei ghts [#weight1][8:0] Wei ghts [#weight0][8:0] Sequentially load Weights and Biases Sequentially load Inputs and initiate ANN Computataion Store Output Update/Initialize Status Signal Compute Layer LayerDone? DNNDone? Yes Yes No No (a) Data Read/Write Order (b) Operartion Flowchart Fig. 3. DNN accelerator data flow and order to initialise the loading data. memory and FIFO buffers for temporary storage. An efficient addressing strategy for neuron-wise weight and bias access is illustrated in Fig. 4 and is defined using the total number of layers L, the number of neurons in the lth layer N(l), and the number of inputs to that layer J(l). Since the number of neurons in one layer determines the number of inputs to the subsequent layer, these parameters satisfy J(l + 1) = N(l)(1) Each parameter address consists of a layer identifier, a select bit indicating whether the accessed parameter is a weight or a bias, and a memory address field, as shown in Fig. 4(a). The select bit distinguishes between weight and bias access, while the most significant bits encode the layer index. The remaining bits represent either the neuron index (for bias) or the combined neuron and input index (for weight), as depicted in Fig. 4(b). The required address length for weights and biases in a layer is therefore given by R addr (l) =⌈log 2 N(l)⌉ +⌈log 2 J(l)⌉(2) and that layer’s overall address width turns into Addr(l) =⌈log 2 L⌉ + 1 + R addr (l)(3) a fixed address width, which is chosen based on the maximum required across all levels, which is specified as R addr = max l=1,2,...,L ⌈log 2 N(l)⌉ +⌈log 2 J(l)⌉(4) and the length of the final uniform address is Addr =⌈log 2 L⌉ + 1 + R addr (5) In addition to providing effective, conflict-free access to weight and bias memories for scaled DNN implementations, this technique enables consistent addressing. Log2(L) Bits 1 Bit Max[R_addr(l)] Layer BitsSelect BitsWeight/Bias RAM Address Addr(l)-1 to Addr(l)-Log2(L) (Layer B its) Addr(l)-Log2(L)-1 (Select Bits) Max[R_addr(l)]-1 to 0 (Weight/Bias RAM Address) R_addr(l)-1 to W_addr(l) W_addr(l)-1 to 0 R_addr(l)-1 to 0 Weight RAM Address Bias RAM Address '0' '1' (a) (b) Fig. 4. Memory mapping scheme for address bits that requires addressing weights and bias for the individual neurons. E. Time-Multiplexed Multi-Activation-Function Integration To address the underutilization of activation-function hard- ware observed in prior accelerators [3], [11], the proposed ar- chitecture integrates a time-multiplexed multi-AF block shared across all PEs. The multi-AF block supports a broad set of nonlinear functions, including Sigmoid, Tanh, SoftMax, GELU, Swish, ReLU, and SELU, using common CORDIC resources and mode-specific datapaths. By multiplexing activation computation in time rather than dedicating separate hardware blocks, the architecture achieves high utilisation factors while incurring minimal area and power overhead. Activation execution is overlapped with vector- engine computation wherever possible, ensuring that the multi- AF block does not become a performance bottleneck despite being shared. F. Scalability and System Integration The proposed vector engine is designed for seamless scal- ability across edge and embedded platforms. By adjusting the number of PEs, memory bank sizes, and iteration depth, the architecture can be tailored to a wide range of performance and energy targets. Furthermore, the modular organisation of the vector engine, control logic, and peripheral units facili- tates automated generation through a synthesizable hardware framework, enabling rapid design-space exploration and de- ployment. Overall, the architecture combines runtime adaptability, high hardware utilisation, and scalable performance, forming a unified compute substrate that bridges the gap between fixed- approximation accelerators and fully accurate but resource- intensive designs. I. CIRCUIT IMPLEMENTATION This section details the circuit-level design of the proposed iterative CORDIC-based MAC unit and the time-multiplexed multi-activation-function (multi-AF) block. The design ob- jective is to achieve a balance between hardware efficiency, numerical accuracy, and runtime configurability while main- taining compatibility with standard deep learning workloads. 5 RegRegReg LUT MUX MUXMUX MUX MUX MUX Xo [N:0] Yo [N:0]Zo [N:0] Xn [N:0]Yn [N:0]Zn [N:0] sgn [Zn-1] μαn αn >>k>>k Fig. 5. Iterative low-latency CORDIC-based MAC architecture with runtime- configurable iteration depth. A. Runtime-Adaptive Iterative CORDIC-Based MAC The proposed MAC unit is based on the unified CORDIC formulation originally introduced by Walther, which supports circular, linear, and hyperbolic computations using only shift, add/subtract, and multiplexing operations. Recent works such as ReCON [5] and Flex-PE [3] have demonstrated the ap- plicability of CORDIC arithmetic to deep learning opera- tions, including MAC, Sigmoid, Tanh, and SoftMax [25]. However, these designs primarily employ pipelined or fixed- stage CORDIC architectures, which impose a static trade-off between accuracy and latency. In contrast, the proposed MAC adopts an iterative CORDIC structure, as illustrated in Fig. 5, where the number of active iterations directly determines the approximation error and execution latency. This enables runtime switching between approximate and accurate execution modes without altering the hardware structure or introducing auxiliary correction logic. The MAC unit supports both 8-bit and 16-bit fixed-point precision modes. In approximate mode, the MAC completes 8-bit and 16-bit operations in 4 and 7 clock cycles, respec- tively, incurring approximately 2% accuracy degradation at the application level. In accurate mode, additional iterations are enabled, completing 8-bit and 16-bit operations in 5 and 9 cycles with less than 0.5% accuracy loss. Additionally, it supports 4-bit modes with accurate 4-bit cycle operation. These operating points are selected based on an accuracy- sensitivity heuristic [3], enabling layer-wise configuration based on numerical criticality. From a circuit perspective, the iterative MAC minimises area and static power by reusing a single CORDIC datapath across iterations, rather than replicating pipeline stages. This design choice reduces the number of adders, shifters, and reg- isters compared to pipelined alternatives, while still enabling high throughput at the vector-engine level through parallelism across multiple PEs. Fig. 6. Hardware AAD module for two inputs. Fig. 7. Hardware AAD module architecture based on sliding window B. Latency Hiding Through Vector-Level Parallelism Although the iterative MAC incurs a multi-cycle latency per operation, this overhead is effectively hidden at the vector- engine level. Since multiple PEs operate concurrently on in- dependent data elements, the increased per-MAC latency does not limit overall throughput for sufficiently large vector widths. This execution model distinguishes the proposed architecture from fully parallel or systolic-array designs, which require deeply pipelined datapaths to sustain throughput and therefore incur higher area and power overheads. The ability to trade per-MAC latency for reduced hardware complexity is particularly advantageous for edge AI accelera- tors, where area and energy efficiency are often more critical than single-operation latency. C. Absolute Average Deviation (AAD) Pooling Block In addition to the MAC and activation units, the vector engine integrates peripheral components such as an Ab- solute Average Deviation (AAD) pooling unit [26] and a normalisation block. The AAD pooling unit is selected due to its favourable accuracy characteristics for CORDIC-based computation, demonstrating a 0.5-1% accuracy improvement over conventional pooling methods with lower computational complexity [3], [26]. Division, subtraction, and absolute value computation are the three primary steps of the hardware implementation of the two inputs in Average Absolute Deviation (AAD) unit as shown in Fig. 6. Initially, the two input values are fed into a subtractor to determine their difference. The subtraction result is then processed through two parallel paths. A comparator receives the result from one path and compares it to zero to identify the sign of the difference, returning either +1 or - 1. To match its timing with the comparator output, the other 6 Fig. 8. Hardware AAD module architecture based on parallel computation. Fig. 9. Multiple feature computations in parallel in hardware. channel passes the subtraction result through a buffer. These two outputs are multiplied, ensuring the final result is always non-negative regardless of the input order, effectively yielding the absolute deviation. This absolute deviation is then divided by two to obtain the final AAD output for the two-input case. For multi-input scenarios, multiple subtraction-absolute (SA) modules operate in parallel, each computing the absolute deviation between pairs of input values as shown in the Fig. 8. The outputs of these SA modules are summed using an adder network, and the accumulated result is divided by the normalisation factor M = N (N-1) to produce the overall AAD value, which is carried out in parallel as shown in Fig. 9. A sliding window technique, in which a window moves over the input data with a specified stride and pooling size, is used to simplify the hardware. To reduce hardware complexity, a sliding window approach is adopted, with a window moving across the input data according to the defined stride and pooling size. Within each window, deviations between data points are computed, accumulated in registers, and normalised to produce the final AAD result efficiently as illustrated in Fig. 7. D. Time-Multiplexed Multi-Activation-Function Block Activation functions represent a small fraction of total oper- ations but often consume disproportionate hardware resources. To address this inefficiency, the proposed design integrates a time-multiplexed multi-AF block that reuses CORDIC hard- ware across multiple nonlinear functions as shown in Fig. 10. The multi-AF block supports Sigmoid, Tanh, SoftMax, GELU, Swish, ReLU, and SELU, enabling compatibility with both CNN and transformer-style workloads. The multi-AF block operates in two primary modes: a hyperbolic rotation (HR) mode for functions that require sinh and cosh computations, and a linear-division (LV) mode for functions that involve normalisation or exponential scaling. By selectively enabling only the required datapaths for a given function, the design achieves utilisation factors of up to 86% in HR mode and approximately 72% in LV mode. Additional auxiliary logic includes a lightweight switching multiplexer for Sigmoid and Tanh selection, a ReLU bypass buffer, a FIFO for intermediate SoftMax storage, and two small multipliers [27] to support GELU computation. Collectively, these components incur less than 4% additional area and power overhead while significantly improving overall hardware util- isation. E. Peripheral Support and Integration The proposed vector engine is integrated as a complete edge-AI processing subsystem comprising a lightweight con- trol engine, on-chip memory banks, input pre-processing logic, and a host communication interface. The control engine uses configuration registers, status flags, and a finite-state machine to control memory addressing, instruction sequencing, and synchronisation, coordinating execution across the MAC array, activation block, and pooling units. Layer-adaptive execution is made easier by runtime control signals such as ComputeInit, LayerDone, and ComputeDone. This enables the reuse of hardware resources across multiple network levels, thereby guaranteeing proper data ordering. A data prefetcher retrieves input feature maps from external memory, buffers them lo- cally, and then broadcasts them to processing components. Index-controlled multiplexing is used to transport intermediate outputs to later layers. To facilitate continuous data feeding and overlapping memory access with computation, parameter storage is managed via partitioned kernel memory banks that independently store activations and weights. The memory interface supports synchronous valid-data loading with a data- ready completion signal, allowing the host processor [28] to capture final outputs without stalling the compute pipeline. All processing elements share a time-multiplexed multi-activation- function unit that uses common CORDIC resources to perform nonlinear operations. To prevent performance bottlenecks, its operations overlap with MAC computation. In addition, integrated pooling and normalisation blocks process partial sums before output generation, reducing intermediate storage and external memory traffic. The modular organisation of con- trol, memory, and peripheral compute stages enables scalable deployment across FPGA and ASIC platforms. It supports efficient system-level integration with embedded processors through a lightweight interface, thereby transforming the vec- tor engine from a standalone compute core into a deployable edge-AI accelerator. IV. EXPERIMENTAL METHODOLOGY To ensure a rigorous, fair, and reproducible evaluation, the proposed vector engine is validated using a structured hardware-software co-design methodology spanning algorith- mic emulation, RTL-level verification, FPGA prototyping, 7 Fig. 10. Time-multiplexed Activation function with integrated data flow and control signals. and ASIC synthesis. The evaluation framework is designed to isolate the impact of iterative CORDIC approximation while maintaining consistent experimental conditions across all comparisons. A. Software-Level Functional Emulation At the algorithmic level, an iso-functional software model of the proposed vector engine is developed in Python 3.0. The model emulates the vector engine’s custom iterative CORDIC arithmetic, precision-switching behaviour, and ex- ecution scheduling. Fixed-point arithmetic is implemented using the FxP-Math library, while neural network layers and quantised inference flows are modelled using QKeras 2.3. The software framework supports configurable precision modes (8-bit and 16-bit), variable CORDIC iteration depth, and layer-wise execution control. All deep learning evalua- tions are performed against an FP32 reference baseline under identical network topology, dataset, and inference conditions. This approach ensures that observed accuracy differences are attributable solely to arithmetic approximation, not to changes in training or model structure. Accuracy is evaluated at both the layer and end-to-end model levels for representative CNN and transformer-style MLP workloads. The number of CORDIC iterations per layer is selected using an accuracy-sensitivity heuristic [3], which identifies numerically critical layers and assigns them to accurate execution modes, while non-critical layers operate in approximate mode. B. RTL Modelling and Functional Verification The proposed iterative CORDIC-based MAC unit and vector-engine datapath are modelled in synthesizable Verilog HDL. The architecture is parameterised to support different vector widths, precision modes, and iteration depths. A cycle- accurate RTL testbench is developed to validate functional correctness across all supported operating modes. Functional verification is performed using Synopsys VCS, where RTL outputs are compared against the software emula- tion model for a wide range of randomised and application- driven test vectors. This cross-validation ensures bit-level consistency between the software model and the hardware im- plementation, accounting for fixed-point rounding, truncation, and iteration control. C. FPGA Prototyping and Measurement FPGA-based evaluation is conducted using the AMD Virtex-707 (VC707) platform. Synthesis, placement, and rout- ing are performed using the AMD Vivado Design Suite with a target operating frequency of 100 MHz. All reported FPGA metrics, including lookup tables (LUTs), flip-flops (FFs), timing, and power consumption, are obtained from post-place- and-route reports to avoid optimistic estimation. To enable fair comparison with state-of-the-art designs, either the reported post-implementation results from prior work are used directly, or the designs are re-synthesised under comparable constraints where feasible. Power measurements are extracted using vendor-supported power analysis tools with realistic switching activity derived from application traces. D. ASIC Synthesis and Technology Assumptions ASIC evaluation is carried out using Synopsys Design Com- piler targeting a commercial 28 nm HPC+ CMOS technology at 0.9 V. Standard-cell libraries for worst-case timing corners are used to ensure conservative delay estimates. Area, timing, and power metrics are extracted from post-synthesis reports. System-level performance metrics, including energy effi- ciency (TOPS/W) and compute density (TOPS/m 2 ), are derived using consistent workload assumptions across all designs. The same precision mode, vector width, and clock frequency normalisation are applied when comparing against prior accelerators to ensure fairness. E. System-Level Deployment and End-to-End Validation To validate practical applicability, the proposed vector en- gine is deployed on a Pynq-Z2 platform with an ARM Cortex- A9 host processor. The accelerator is integrated through an AXI-based interface and evaluated on object detection and classification workloads. End-to-end latency and power con- sumption are measured at the application level, capturing the 8 TABLE I COMPARATIVE PERFORMANCE METRICS FOR CORDIC-BASED DIFFERENT SOTA MAC UNITS DesignTCAS-I’24 [29]ISCAS’25 [4]ICIIS’25 [11]TVLSI’25 [30]TCAD’22 [31]TVLSI’25 [3]Proposed FPGA Utilization (VC707, 100 MHz) ParameterFP32FP32BF16Posit-8VedicWallaceBoothQuant-MACCORDICMSDF-MACAcc-App-MACCORDICIter-MAC LUTs80658054367046716010684725662574524 FFs1072171832417524111359567245NR3722 Delay (ns)5.564.60.5122.684.52.63.15.41.523.23.514.59.1 Power (mW)378296136686.13.33.14.28.35.86.921.9 PDP (pJ)21021361.669.618227.458.589.622.6812.618.5624.2917.29 ASIC Performance (28nm, 0.9V) Area (umˆ2)100001300043407544072962711752642862598570108 Delay (ns)67970029540.66.385.625.33.582.361.422.60.72.98 Power (mW)15.8629.36.891.8353712.88924.56.712.41.56.3 PDP (pJ)10768.942051046821189223.3207.9467.84318.6257.829.51432.241.0518.774 TABLE I COMPARATIVE PERFORMANCE METRICS FOR CORDIC-BASED DIFFERENT SOTA AF UNITS DesignISQED’24 [32]TCAS-I’20 [33]TVLSI’23 [34]ISQED’24 [32]TC’23 [35]ISQED’24 [32]TVLSI’25 [3]Proposed FPGA Utilization (VC707, 100 MHz) ParameterSoftmax-FP32Softmax-FP16Softmax-BF16Softmax- FxP8/16Softmax-16bTanh-FP32Tanh-FP16Tanh-BF16Tanh/Sigmoid-16bSigmoid-FP32Sigmoid-FP16Sigmoid-BF16SSTpFxP-4/8/16 LUTs321711371263256412154298153015132395510118531856897537 FFsNRNRNR27941012NRNRNR1503NRNRNR1231468 Delay (ns)9243452.33.325634380.18109604511.82.6 Power (mW)11511577NR16513012482681121118835930 PDP (pJ)1058049453465-5487280421631161231318970803735696.278 ASIC Performance (28nm, 0.9V) Area (umˆ2)41536172891130118392381950601180843870523223418551180491522138 Delay (ns)643.30.31.643.33.4NR7.64.43.262.32.6 Power (mW)75402551.61.68.7532150104.82.55.260 PDP (pJ)45016082.515.52.56359.96.8-7621.128.1511.96156 combined effects of computation, data movement, and control overhead. This multi-level evaluation methodology ensures that the reported improvements are not limited to isolated circuit optimisations but translate into tangible system-level benefits for real-world edge AI deployments. V. RESULTS AND DISCUSSION This section presents a comprehensive evaluation of the proposed CORDIC-based vector engine at the circuit, archi- tectural, and system levels. Results are reported for FPGA prototyping, ASIC synthesis, and end-to-end deployment and are compared against representative state-of-the-art (SoTA) AI accelerators to highlight performance, energy efficiency, and scalability trade-offs. A. MAC-Level Hardware Efficiency Table I compares the proposed iterative CORDIC- based MAC unit with prior CORDIC, logarithmic, and approximation-based MAC designs across both FPGA and ASIC platforms. On the Virtex-707 FPGA, the proposed MAC achieves significant reductions in lookup tables (LUTs) and flip-flops (FFs) compared to pipelined CORDIC and fixed- point MAC designs, while avoiding the use of DSP blocks. This reduction directly translates into lower static power consumption and improved placement flexibility. At the ASIC level (28 nm, 0.9 V), the proposed MAC demonstrates up to 33% reduction in critical-path delay and approximately 21% lower power per MAC stage compared to comparable CORDIC-based designs. Although the iterative MAC incurs a multi-cycle execution latency, this overhead is amortised at the vector-engine level through parallel execu- tion across multiple processing elements (PEs), as discussed in Section I. Consequently, the proposed design achieves a favourable power-delay product (PDP) while maintaining runtime configurability between approximate and accurate execution modes. B. Activation-Function Hardware Utilization Table I summarises the FPGA and ASIC resource util- isation of the proposed time-multiplexed multi-activation- function (multi-AF) block relative to prior dedicated AF imple- mentations. Existing designs often allocate separate hardware blocks for individual activation functions [36], leading to significant underutilization and dark silicon. In contrast, the proposed multi-AF block reuses CORDIC resources across multiple nonlinear functions, including Sigmoid, Tanh, Soft- Max, GELU, Swish, ReLU, and SELU. The results show that the proposed design achieves utili- sation factors of 72-86% depending on the activation mode, while incurring less than 4% additional area and power over- head. On an FPGA, the multi-AF block reduces LUT and F usage compared to SoTA designs supporting a similar function set. On ASIC, it demonstrates lower power consumption and competitive delay, confirming that time multiplexing effec- tively mitigates activation-function underutilization without compromising performance. C. Accuracy Evaluation Under Iterative Approximation Fig. 11 reports the accuracy of representative CNN and DNN models under different CORDIC iteration settings. The results confirm that numerical error is tightly coupled to 9 0 10 20 30 40 50 60 70 80 90 100 Conv-4bProp-4bConv-8bProp-8bConv-16bProp-16bConv-32bProp-32b Classification Accuracy (%) signed fixed-point precision (bitwidth) Custom/MNISTLeNet-5/MNISTResNet-18/MNISTCaffeNet/MNISTVGG-16/CIFAR-10 VGG-16/CIFAR-100LeNet-5/CIFAR-10ResNet-18/CIFAR-10ResNet-18/CIFAR-100CaffeNet/ImageNet Fig. 11.Evaluation of DNN accuracy for different DNN models with CORDIC methodology. the number of active CORDIC iterations, validating the ef- fectiveness of the proposed runtime accuracy-latency trade- off mechanism. When operating in approximate mode, the accelerator incurs approximately 2% accuracy degradation, while accurate mode limits accuracy loss to below 0.5%. Importantly, by applying an accuracy-sensitivity heuristic to select the iteration depth per layer, most of the perfor- mance benefits of approximate execution are retained while preserving end-to-end model accuracy. This demonstrates that the proposed architecture enables fine-grained control over numerical fidelity without requiring retraining or auxiliary correction hardware. D. FPGA System-Level Comparison Table IV compares the proposed vector engine against SoTA FPGA-based AI accelerators using object detection work- loads such as TinyYOLO-v3. The proposed design achieves competitive throughput while significantly reducing power consumption. Operating at 85.4 MHz on the Virtex-707 plat- form, the vector engine delivers 6.43 GOPS/W at only 0.53 W, outperforming several prior designs in energy efficiency despite using no DSP blocks. Compared to designs such as Flex-PE and LPRE, which rely on higher operating frequencies or specialised arithmetic units, the proposed architecture emphasises energy efficiency and scalability, making it particularly well-suited for edge deployments where power budgets are tightly constrained. E. ASIC Scalability and Compute Density ASIC-level scalability is evaluated using two configurations of the proposed vector engine: a 64-PE configuration and a 256-PE configuration, as reported in Table V. The 64-PE configuration serves as a computationally equivalent baseline, demonstrating comparable performance to prior designs at significantly lower area and power. The 256-PE configuration represents a resource-equivalent comparison, achieving a peak compute density of 4.83 TOPS/m 2 and an energy efficiency of 11.67 TOPS/W. Fig. 12. Prototype visualisation, showing Pynq-z2 for edge AI inference on Unmanned Aerial Vehicles (UAV). These results highlight the benefits of the proposed iterative execution model, where increased vector width compensates for per-MAC latency while preserving energy efficiency. The architecture’s scalability enables efficient deployment across a wide range of performance targets without redesigning the core datapath. F. End-to-End Embedded Deployment Fig. 13 presents a layer-wise execution-time and power breakdown for the VGG-16 model, illustrating the impact of runtime precision switching on system performance. End-to- end deployment on a Pynq-Z2 platform with an ARM Cortex- A9 host reports a total latency of 84.6 ms at 0.43 W for object detection and classification workloads, as shown in Fig. 12. It outperforms prior works: [3] (186.4ms / 2.24 W on V C707), [40] (772 ms / 1.524 W on V C707), [4] (184 ms / 0.93 W on Pynq-Z2), [6] (163.7 ms / 13.32 W on V CU102), and baselines such as NVIDIA Jetson Nano (226 ms / 1.34 W) and Raspberry Pi (555 ms / 2.7 W). The proposed vector engine achieves lower latency and lower power consumption than prior FPGA-based accelerators and commercial embedded platforms such as the NVIDIA Jetson Nano and Raspberry Pi. These improvements stem from a combination of iterative MAC efficiency, reduced memory bandwidth requirements, and dynamic precision adaptation. Overall, the results demonstrate that the proposed archi- tecture delivers consistent improvements across circuit-level efficiency, architectural scalability, and system-level perfor- mance, validating its suitability for energy-efficient edge AI acceleration. VI. CONCLUSION AND FUTURE WORK This paper presented a runtime-adaptive, CORDIC- accelerated vector engine designed to address the efficiency and flexibility challenges of deep learning inference on resource-constrained edge platforms. By introducing a low- resource, iterative CORDIC-based MAC unit with runtime- configurable iteration depth, the proposed architecture enables 10 TABLE IV ANALYSIS OF FPGA HARDWARE IMPLEMENTATION FOR OBJECT DETECTION (TINYYOLO-V3) WITH SOTA AI ACCELERATOR DESIGNS DesignPlatformPrecisionk-LUTsk-Regs/FFsDSPs Op. Freq (MHz) Energy efficiency (GOPS/W) Power(W) ProposedVC7074/8/1626.715.9-85.46.430.53 TVLSI’25 [3]VC7074/8/16/3238.717.4734668.422.24 TCAS-I’24 [37]ZU3EG840.845.52581000.392.2 TCAS-I’23 [38]XCVU9P813239.5961506.365.52 TVLSI’23 [39]ZCU1028117741323004.26.58 Access’24 [2]VC7074/819.812.1391360.681.81 ISCAS’25 [4]VCU1298/16/3217.514.8-54.52.641.6 TABLE V ASIC PERFORMANCE COMPARISON WITH SOTA 8-BIT ACCELERATOR DESIGNS, WITH CMOS 28NM, 0.9V, SF TECHNOLOGY. DesignNetwork/ArchDatatypeFreq. (GHz)Area (m 2 )Power (mW) Energy Efficiency TOPS/W Compute Density TOPS/m 2 TCAS-I’24 [29]Vector Engine (64×MACs)FP8 1.470.89616227.242.39 1.291.1813753.571.21 TCAS-I’22 [1] Vector Engine (64×MACs) 196-64-32-32-10 INT-80.42.43224.67.751.67 ISCAS’25 [4] TREA (64×MACs) 196-64-32-32-10 Posit-81.256.73230.47.550.16 TVLSI’25 [3]Systolic Array (8x8)FxP80.441.855234.32.76 ICIIS’25 [11] Layer-Reused (64×MACs) 196-64-32-32-10 FxP80.253.7815404.282.07 Proposed Vector Engine 64×PEs FxP-4/8/16 1.240.433293.841.52 Vector Engine 256×PEs0.961.42118611.674.83 Access’24 [2] Shared Bank (256×MACs) 784-196-120-84-10 FxP80.281.58499.76.871.18 0 4 8 12 16 20 0 7 14 21 28 35 42 49 56 63 70 Execution Time (us) Power Consumption (mW) Fig. 13. VGG-16 layer-wise execution time and power consumption. fine-grained trade-offs between accuracy and latency with- out requiring auxiliary error-correction hardware or structural modifications. In contrast to prior fixed-approximation designs, this approach allows dynamic adaptation to layer-level numer- ical sensitivity while maintaining compatibility with standard deep learning workloads. The proposed vector engine further integrates a time- multiplexed multi-activation-function (multi-AF) block that significantly improves hardware utilisation and mitigates dark silicon. By sharing CORDIC resources across a wide range of nonlinear functions, including Sigmoid, Tanh, SoftMax, GELU, Swish, ReLU, and SELU, the architecture achieves high utilisation factors with minimal additional area and power overhead. This balanced treatment of MAC and activation units addresses a persistent inefficiency in existing deep learning accelerators. Comprehensive evaluation across software emulation, RTL verification, FPGA prototyping, and 28 nm ASIC synthesis demonstrates the effectiveness of the proposed design. The iterative MAC unit achieves up to 33% reduction in critical- path delay and 21% power savings per stage, while scalable vector-engine configurations deliver a peak compute density of 4.83 TOPS/m 2 and an energy efficiency of 11.67 TOPS/W. End-to-end deployment on embedded platforms further con- firms that the architectural benefits translate into tangible improvements in latency and power consumption at the system level. Future work will focus on extending the proposed frame- work toward a compiler-assisted design flow that automates layer-wise precision and iteration selection based on model sensitivity analysis. In addition, integrating full physical design and place-and-route (PnR) optimisation will enable more ac- curate post-layout evaluation and facilitate tape-out readiness. Further exploration of adaptive execution strategies for emerg- ing transformer and multi-modal workloads, as well as tighter integration with RISC-V-based system-on-chip platforms, rep- resents promising directions for expanding the applicability of the proposed vector engine [28]. Overall, the proposed runtime-adaptive CORDIC-based vec- 11 tor engine provides a scalable and energy-efficient compute substrate that bridges the gap between approximate and ac- curate deep learning acceleration, making it well-suited for next-generation edge AI systems. REFERENCES [1] R. Pilipovi ́ c, P. Buli ́ c, and U. Lotri ˇ c, “A Two-Stage Operand Trimming Approximate Logarithmic Multiplier,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 68, p. 2535–2545, June 2022. [2] N. Ashar, G. Raut, V. Treevedi, S. K. Vishvakarma, and A. Ku- mar, “QuantMAC: Enhancing Hardware Performance in DNNs With Quantize Enabled Multiply-Accumulate Unit,” IEEE Access, vol. 12, p. 43600–43614, 2024. [3] M. Lokhande, G. Raut, and S. K. Vishvakarma, “Flex-PE: Flexible and SIMD Multiprecision PE for AI Workloads,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 33, p. 1610–1623, June 2025. [4] O. Kokane, M. Lokhande, G. Raut, A. Teman, and S. K. Vishvakarma, “LPRE: Logarithmic Posit-enabled Reconfigurable edge-AI Engine,” IEEE International Symposium on Circuits and Systems, 2025. [5] O. Kokane, G. Raut, S. Ullah, M. Lokhande, A. Teman, A. Kumar, and S. K. Vishvakarma, “Retrospective: A CORDIC-Based Configurable Activation Function for N Applications,” in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), p. 1–6, 2025. [6] R. Pilipovi ́ c and P. Buli ́ c, “On the design of logarithmic multiplier using radix-4 booth encoding,” IEEE Access, vol. 8, p. 64578–64590, 2020. [7] Y. Mao and Q. Liu, “Aln: Approximate layer normalization for trans- former training on edge device,” IEEE Transactions on Computers, p. 1–14, 2026. [8] L. Nkenyereye, C. Rajkumar, B. G. Lee, and W.-Y. Chung, “Dynamic transfer learning switching approach using resource benchmark in edge intelligence,” IEEE Internet of Things Journal, vol. 12, no. 13, p. 25148–25170, 2025. [9] M. Lokhande, A. Jain, and S. K. Vishvakarma, “Precision-aware On- device Learning and Adaptive Runtime-cONfigurable AI acceleration,” IEEE International Symposium on VLSI Design and Test, Aug. 2025. [10] A. Jha, T. Dewangan, M. Lokhande, and S. K. Vishvakarma, “QForce- RL: Quantized FPGA-Optimized RL Compute Engine,” IEEE Interna- tional Symposium on VLSI Design and Test (VDAT), Aug. 2025. [11] S. Kumar, K. Gupta, I. S. Dasanayake, M. Lokhande, and S. K. Vishvakarma, “HYDRA: Hybrid data multiplexing and run-time layer configurable dnn accelerator,” in Proceedings of the 19th International Conference on Industrial and Information Systems (ICIIS), (Sri Lanka), Dec. 2025. [12] J.-S. Park, C. Park, S. Kwon, T. Jeon, Y. Kang, H. Lee, D. Lee, J. Kim, H.-S. Kim, Y. Lee, S. Park, M. Kim, S. Ha, J. Bang, J. Park, S. Lim, and I. Kang, “A Multi-Mode 8k-MAC HW-Utilization-Aware Neural Processing Unit With a Unified Multi-Precision Datapath in 4- nm Flagship Mobile SoC,” IEEE Journal of Solid-State Circuits, vol. 58, no. 1, p. 189–202, 2023. [13] M. Verhelst, L. Benini, and N. Verma, “How to Keep Pushing ML Accelerator Performance? Know Your Rooflines!,” IEEE Journal of Solid-State Circuits, p. 1–18, June 2025. [14] A. Krishna, S. Rohit Nudurupati, D. G. Chandana, P. Dwivedi, A. van Schaik, M. Mehendale, and C. S. Thakur, “RAMAN: A Reconfigurable and Sparse tinyML Accelerator for Inference on Edge,” IEEE Internet of Things Journal, vol. 11, p. 24831–24845, July 2024. [15] T. Chaudhari, A. J, T. Dewangan, M. Lokhande, and S. K. Vishvakarma, “XR-NPE: High-throughput mixed-precision simd neural processing engine for extended reality perception workloads,” in 39th International Conference on VLSI Design and 25th International Conference on Embedded Systems (VLSI-D / ES), (Pune, India), Jan. 2026. [16] M. Jaiswal, V. Sharma, A. Sharma, S. Saini, and R. Tomar, “Quantized cnn-based efficient hardware architecture for real-time hand gesture recognition,” Microelectronics Journal, vol. 151, p. 106345, July, 2024. [17] Z. Yuan, Q. Li, X. Lin, T.-M. Grønli, and S. Cherkaoui, “Edge ai for internet of robotic things,” IEEE Internet of Things Magazine, vol. 9, no. 1, p. 4–6, 2026. [18] P. Chen, T. Ouyang, K. Luo, W. Hong, and X. Chen, “Codrone: Autonomous drone navigation assisted by edge and cloud foundation models,” IEEE Internet of Things Journal, vol. 13, no. 4, p. 5593– 5609, 2026. [19] Y. Chen, H. Wang, Z. Li, E. Mou, T. Song, S. Xia, and Y. Pang, “A lightweight uav object detector based on optimized yolov8 fused with an auxiliary learning branch for aiot,” IEEE Internet of Things Journal, vol. 13, no. 4, p. 5793–5808, 2026. [20] M. Ali and K. Nathwani, “Exploiting wavelet scattering transform and 1d-cnn for unmanned aerial vehicle detection,” IEEE Signal Processing Letters, vol. 31, p. 1790–1794, 2024. [21] K. Zhang, X. Liu, K. Wang, Q. Cai, X. Xie, J. Zhang, J. Chen, C. Zhang, X. Tong, Z. Gong, and K. Li, “Edcl: An efficient dynamic continual learning framework for iot systems,” IEEE Transactions on Computers, p. 1–16, 2026. [22] Y.-C. Lin, M.-S. Huang, J.-B. Wang, W.-C. Chen, N.-S. Chang, C.-P. Lin, C.-S. Chen, T.-D. Chiueh, and C.-H. Yang, “A 16nm Fully Inte- grated SoC for Hardware-Aware Neural Architecture Search,” in 2025 IEEE European Solid-State Electronics Research Conference (ESSERC), p. 397–400, 2025. [23] J. Hu, Z. Zhang, Z. Li, Q. Meng, X. Shi, Q. Huang, H. Wang, and S. Chang, “Single-step hardware-aware neural network quantization with mixed precision,” IEEE Transactions on Computers, p. 1–12, 2026. [24] A. Sharma, L. H. Krishna, and B. Srinivasu, “High-Performance Gemmini-Based Matrix Multiplication Accelerator for Deep Learning Workloads,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 33, no. 12, p. 3276–3289, 2025. [25] S. Mehra, G. Raut, R. D. Purkayastha, S. K. Vishvakarma, and A. Bi- asizzo, “An empirical evaluation of enhanced performance softmax function in deep learning,” IEEE Access, vol. 11, p. 34912–34924, 2023. [26] K. Khalil, O. Eldash, A. Kumar, and M. Bayoumi, “Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Ac- celerator,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 30, p. 303–314, Mar. 2022. [27] W. Zhang, X. Geng, X. Hu, H. Wang, J. Jiang, Q. Wang, S. Liu, J. Han, and H. Jiang, “Lut-alms: Trading off accuracy and power for approximate logarithmic multipliers via lut optimization,” IEEE Transactions on Computers, p. 1–14, 2026. [28] A. Kamaleldin, H. Aouinti, and D. G ̈ ohringer, “Procon-v: A pro- grammable tightly coupled convolution accelerator based on risc-v custom instructions for edge devices,” IEEE Transactions on Computers, p. 1–15, 2026. [29] B. Li, K. Li, J. Zhou, Y. Ren, W. Mao, H. Yu, and N. Wong, “A Reconfig- urable Processing Element for Multiple-Precision Floating/Fixed-Point HPC,” IEEE Trans. Circuits Syst. I, Exp. Briefs, vol. 71, p. 1401–1405, Mar. 2024. [30] S. M. Cherati, M. Barzegar, and L. Sousa, “MSDF-Based MAC for Energy-Efficient Neural Networks,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., p. 1–12, 2025. [31] S. Ullah, S. Rehman, M. Shafique, and A. Kumar, “High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Ac- celerators,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 41, p. 211–224, Feb. 2022. [32] M. Basavaraju, V. Rayapati, and M. Rao, “Exploring Hardware Ac- tivation Function Design: CORDIC Architecture in Diverse Floating Formats,” in 25th International Symposium on Quality Electronic Design (ISQED), p. 1–8, 2024. [33] D. Zhu, S. Lu, M. Wang, J. Lin, and Z. Wang, “Efficient Precision- Adjustable Architecture for Softmax Function in DL,” IEEE Trans. Circuits Syst. I, Exp. Briefs, vol. 67, p. 3382–3386, Dec. 2020. [34] K. Chen, Y. Gao, H. Waris, W. Liu, and F. Lombardi, “Approximate Softmax Functions for Energy-Efficient DNNs,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 31, p. 4–16, Jan. 2023. [35] N. A. Mohamed and J. R. Cavallaro, “A Unified Parallel CORDIC- Based Hardware Architecture for LSTM Network Acceleration,” IEEE Transactions on Computers, vol. 72, p. 2752–2766, Oct. 2023. [36] J. Kim, K. Choi, and I.-C. Park, “Hardware-efficient unified approx- imation for implementing diverse smooth activation functions,” IEEE Transactions on Computers, p. 1–8, 2026. [37] B. Wu, T. Yu, K. Chen, and W. Liu, “Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 71, p. 1285–1298, Mar. 2024. [38] S. Ki, J. Park, and H. Kim, “Dedicated FPGA Implementation of the Gaussian TinyYOLOv3 Accelerator,” IEEE Trans. Circuits Syst. I, Exp. Briefs, vol. 70, p. 3882–3886, Oct. 2023. [39] W. Lee, K. Kim, W. Ahn, J. Kim, and D. Jeon, “A Real-Time Object Detection Processor With XNOR-based Variable-Precision Computing Unit,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 31, p. 749–761, June 2023. [40] G. Raut, S. Karkun, and S. K. Vishvakarma, “An Empirical Approach to Enhance Performance for Scalable CORDIC-Based DNNs,” ACM Trans. Reconfigurable Technol. Syst., vol. 16, June 2023.