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Hardware-Efficient FPGA Implementation of Sigmoid Function Using Mixed-Radix Hyperbolic Rotation CORDIC
Chintan Panchal, Ankur Changela, Mohendra Roy
Intelligence
Status: succeeded | Model: Gemma-4-26B-A4B | Prompt: intel-v1 | Confidence: 97%
Last extracted: 6/21/2026, 7:02:16 AM
Summary
This paper proposes a hardware-efficient FPGA implementation of the sigmoid activation function using a three-stage Mixed-Radix Hyperbolic Rotation CORDIC (MR-HRC) architecture. The design leverages the mathematical relationship between the sigmoid and hyperbolic tangent (tanh) functions, normalizing the input range to ±1 to map the tanh computation to a reduced range of ±0.5. The architecture combines a radix-2 stage for stable convergence and a radix-4 stage for accelerated convergence without requiring scale-factor compensation. A final Radix-2 Linear Vectoring CORDIC (R2-LVC) stage computes the tanh value. Implemented on a Xilinx Virtex-7 FPGA with 16-bit fixed-point representation, the design achieves a mean absolute error of 4.23e-4 while utilizing only 835 logic slices and zero DSP slices.
Entities (6)
Relation Signals (4)
Radix-2 Linear Vectoring CORDIC → computes → Hyperbolic Tangent
confidence 100% · In the final stage, a radix-2 linear vectoring CORDIC (R2-LVC) is used to compute the hyperbolic tangent
Xilinx Virtex-7 FPGA → hosts → Mixed-Radix Hyperbolic Rotation CORDIC
confidence 100% · The design is realized on an Xilinx Virtex-7 FPGA using a 16-bit fixed-point representation.
Mixed-Radix Hyperbolic Rotation CORDIC → implements → Sigmoid Function
confidence 100% · The proposed approach leverages the mathematical relationship between the sigmoid and hyperbolic tangent functions... using a mixed-radix CORDIC-based architecture.
Sigmoid Function → isusedin → Artificial Neural Networks
confidence 100% · The sigmoid activation function is widely used for probabilistic output, binary classification, and gating mechanisms in recurrent neural networks
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Abstract
Abstract:Efficient hardware implementation of nonlinear activation functions is a crucial task in deploying artificial neural networks on resource-constrained and edge devices such as Field-Programmable Gate Arrays (FPGAs). The sigmoid activation function is widely used for probabilistic output, binary classification, and gating mechanisms in recurrent neural networks, despite its reliance on exponential computations. This paper presents a hardware-efficient FPGA implementation of the sigmoid activation function using a mixed-radix CORDIC-based architecture. The proposed approach leverages the mathematical relationship between the sigmoid and hyperbolic tangent functions. The input range is normalized to 1, enabling the corresponding tanh computation to operate within a reduced range of 0.5, which significantly improves convergence behavior. To achieve high accuracy with minimal hardware overhead, a modified mixed-radix hyperbolic rotation CORDIC (MR-HRC) algorithm combining radix-2 and radix-4 iterations is introduced. The initial radix-2 stage ensures stable convergence, while the subsequent radix-4 stage accelerates convergence without requiring scale-factor compensation. In the final stage, a radix-2 linear vectoring CORDIC (R2-LVC) is used to compute the hyperbolic tangent by dividing hyperbolic sine and cosine values derived from the MR-HRC algorithm. The entire architecture is fully pipelined and implemented on an FPGA. The design is realized on an Xilinx Virtex-7 FPGA using a 16-bit fixed-point representation. Experimental results demonstrate a significant reduction in hardware utilization, requiring only 835 logic slices with zero DSP usage. Additionally, the design achieves a mean absolute error of 4.23 10^-4, outperforming several recent sigmoid implementations.
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- Source: https://arxiv.org/abs/2604.23547v1
- Canonical: https://arxiv.org/abs/2604.23547v1
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11institutetext: Pandit Deendayal Energy University, Gujarat, India 11email: Corresponding authors: Ankur.Changela@sot.pdpu.ac.in and mohendra.roy@ieee.org Hardware-Efficient FPGA Implementation of Sigmoid Function Using Mixed-Radix Hyperbolic Rotation CORDIC Chintan Panchal Ankur Changela Mohendra Roy Abstract Efficient hardware implementation of nonlinear activation functions is a crucial task in deploying artificial neural networks on resource-constrained and edge devices such as Field-Programmable Gate Arrays (FPGAs). The sigmoid activation function is more popular among researchers for probabilistic output, binary classification, and gating mechanisms in recurrent neural networks, despite its exponential computations. This paper presents a hardware-efficient FPGA implementation of the sigmoid activation function using a mixed-radix CORDIC-based architecture. The proposed approach uses the mathematical relationship between the sigmoid and hyperbolic tangent functions. The input range is normalized to ±1± 1, enabling the corresponding Tanh computation to operate within a reduced range of ±0.5± 0.5, which significantly improves convergence behavior. To achieve high accuracy with minimal hardware overhead, a modified mixed-radix hyperbolic rotation CORDIC (MR-HRC) algorithm combining radix-2 and radix-4 iterations is presented. The initial radix-2 stage ensures stable convergence, while the subsequent radix-4 stage accelerates convergence without the need for scale-factor compensation. Later, the radix-2 linear vectoring CORDIC (R2-LVC) stage is used to compute the hyperbolic tangent by dividing hyperbolic sine and cosine derived using the MR-HRC algorithm. The entire architecture is fully pipelined and implemented on an FPGA. The proposed design is implemented on an Xilinx Virtex-7 FPGA using a 16-bit fixed-point representation. Experimental results demonstrate a significant reduction in hardware utilization, achieving only 835 logic slices with zero DSP usage. Furthermore, the design attains a mean absolute error of 4.23×10−44.23× 10^-4, showing better performance compared to recent sigmoid implementations. 1 Introduction Neuroengineering has made great strides over the past few years, largely due to increasing interest in smaller, faster, cheaper means of providing ANNs through integrated circuits (IC). Neuromorphic hardware is designed to operate similarly to the biological neural networks in the way they process information and produce output. This type of system provides a means to implement ANNs across a much broader application space, including: high-bandwidth video applications, cryptography, IoT, robotics, and telecommunications, where speed, size, and energy efficiency are of utmost importance. Field-Programmable Gate Arrays (FPGAs) are well-suited for these applications due to their ability to support highly parallel computing architectures, shorter development cycles, and lower production costs for medium-scale projects. FPGAs offer advantages over traditional Central Processing Units (CPUs) and Graphics Processing Units (GPUs) in terms of energy efficiency and compact design. However, implementing ANNs directly on FPGAs presents unique challenges, particularly in the computation of neuron activation functions. These challenges stem from the need to balance hardware resource constraints with numerical precision, especially when using fixed-point arithmetic instead of floating-point calculations. Among the various activation functions used in neural networks, the sigmoid function, as shown in Fig. 1 is one of the most widely employed due to its nonlinear properties and ability to map input values to a range between 0 and 1. It plays a crucial role in shallow networks like Multilayer Perceptrons (MLPs) during both inference and training phases, as well as in recurrent neural networks such as Long Short-Term Memory (LSTM) networks and Gated Recurrent Units (GRUs). While Rectified Linear Units (ReLU) and their variants have gained popularity in deep learning applications, the sigmoid function remains essential for tasks involving binary decision-making, probabilistic outputs, and structured attention mechanisms. Figure 1: Sigmoid activation function over a range [−6,6][-6,6] Despite its importance, directly implementing the sigmoid function in hardware is computationally expensive due to the complex operations involved, such as exponentiation and division. This paper addresses this challenge by proposing a novel hardware approximation method for the sigmoid function. The method utilizes a combination of first- and second-degree polynomial functions to approximate the sigmoid curve, with the primary goal of minimizing approximation error while optimizing hardware resource usage. This approach offers a practical solution for deploying efficient and accurate neural activation functions in FPGA-based systems, paving the way for improved performance in neuromorphic applications. 2 Related Work The sigmoid function is a nonlinear component widely used in machine learning as a neural activation function. Artificial neural networks (ANNs) implemented with neuromorphic hardware provide solutions for various applications where high data throughput, small size and less power consumption are required. Field-Programmable Gate Arrays (FPGAs) owns these essential features that are aligned with the requirements. However, due to the trade-off between resource limitations and numerical accuracy, implementing ANNs on FPGAs also poses difficulties, such as the computing of the neuron activation functions. Bosso, V.d.A et.al [1] [1], the authors propose a systematic domain-partitioning strategy for sigmoid approximation that identifies optimal boundaries rather than relying on heuristic or arbitrary segments. This optimization resulted in a low mean absolute approximation error of 1.66×10−31.66×10^-3 by employing 0.04%0.04\% logic blocks and 3.21%3.21\% DSP blocks in a Ciclone V 5CGXFC7C7F23C8 FPGA Device, a marked improvement over previous methods. The architecture relaxes the traditional constraint of power-of-two operands, demonstrating that arbitrary operand values can be utilized without a systematic increase in hardware overhead. The work establishes a rigorous methodological framework by validating results across diverse FPGA architectures from multiple vendors and providing open-source VHDL implementations of all compared designs to ensure reproducibility. The study advocates for a standardized benchmarking process, utilizing consistent bit-widths, synthesis tools, and hardware targets to ensure equitable performance comparisons within the field. Number of papers that have been published on the hardware implementation of the sigmoid function also demonstrate the ongoing interest in studying it. The sigmoid function is commonly implemented using piecewise approximation with linear or nonlinear segments, LUTs for direct output value storage, Taylor series expansion, and Coordinate Rotation Digital Computer (CORDIC) techniques. The study [9] uses CORDIC-based methods to iteratively compute trigonometric and hyperbolic functions with the goal of achieving low maximum approximation error. Nevertheless, this method requires a large amount of chip resources. Similarly, the authors in [5] used the Lagrange form and Taylor’s theorem for approximation. To improve chip space efficiency, the paper also suggests reusing neuron circuitry in the approximation calculation. 3 Proposed Methodology The sigmoid activation function plays a fundamental role in a wide range of artificial intelligence and machine learning (AI/ML) applications. It is extensively used in neural networks for tasks such as binary classification, probabilistic modeling, and gating mechanisms in recurrent architectures. One important aspect of this function is its ability to take an input of any value, whether positive or negative, and translate it into an output value that will only fall within the range of 0 to 1, which can be easily viewed as a probability. This feature enables it to be utilized within the output layers of classifications, logistic regression models, as well as in attention and control units within a system of deep learning. This mathematical definition of this function is presented in (1). σ(x)=11+e−x σ(x)= 11+e^-x (1) The direct hardware implementation of the exponential function involved in the sigmoid is computationally expensive. Many researchers have explored an alternative way that enables efficient implementation while preserving numerical accuracy. The sigmoid can be expressed in terms of tanh as given in (2). σ(x)=12(1+tanh(x2)) σ(x)= 12 (1+ ( x2 ) ) (2) From a design perspective, this identity reduces the process of computing the sigmoid function down to hyperbolic tangent (tanh) evaluation, followed by the operations of a scale and an add. In addition, the hyperbolic tangent (Tanh) can be calculated very efficiently through CORDIC-based architectures, which only require the use of shifting and addition [12]. Therefore, this means that this new approach has significantly reduced the amount of computations needed for the evaluation of sigmoids and eliminated the requirement for both multipliers and exponential units. The proposed method assumes that the input range of the sigmoid activation function will be limited to ±1± 1. The majority of practical AI/ML systems, when developing a neural network model, normalize the input to the neural network to improve the convergence range, thus allowing for better numerical stability. With a limited input range, it is possible to optimise the design of the neural network model to focus on the most relevant region while not sacrificing the performance of the model as a whole. Based on a sigmoid–tanh relationship, the corresponding range for the sigmoid inputs, ±1± 1, is mapped to tanh, with only output values between ±0.5± 0.5. This narrow input range offers a significant advantage when implementing on hardware. The output from tanh will converge quicker with fewer iterations and less error when using iterative algorithms (like CORDIC). Thus, the overall latency, area, and power are reduced when using the sigmoids activation functions versus tanh. The CORDIC algorithm allows for the efficient and hardware-compatible computation of all transcendental functions, including trigonometric and hyperbolic functions [3, 2]. CORDIC was originally designed for navigation systems where real-time response is critical, but it is now particularly useful for modern artificial intelligence and machine learning (AI/ML) hardware accelerators that are based on field programmable gate arrays (FPGAs) and edge devices, this is due to the fact that it uses shift-and-add operations exclusively. Therefore, there is no requirement for either multipliers or complex exponential functions; consequently, CORDIC decreases the area, power, and complexity of designs. In hyperbolic mode, the CORDIC algorithm can be configured to compute sinh and cosh. The hyperbolic tangent can then be obtained as the ratio of these two quantities. In the proposed approach, CORDIC is used to generate tanh within a limited and well-defined input range. As discussed earlier, by expressing the sigmoid function in terms of the hyperbolic tangent, the problem of computing the sigmoid reduces to evaluating tanh(x2)tanh( x2) followed by a simple scaling and offset operation. Since the input range of the sigmoid function is assumed to be limited to [−1,1] [-1,1 ], the corresponding input range for the CORDIC-based tanh computation becomes [−0.5,0.5][-0.5,0.5]. This reduced range significantly improves the convergence behavior of the hyperbolic CORDIC algorithm and allows the number of iterations to be minimized without compromising accuracy. Figure 2: Proposed CORDIC-based methodology organized as a three-stage processing pipeline As shown in Fig.2, the proposed sigmoid realization is organized as a three-stage processing pipeline. The first stage uses a mixed-radix HRC, which accepts initial input (x0=1Kh,y0=0,z0=Zin)(x_0= 1K_h,y_0=0,z_0=Z_in). In this stage, the CORDIC operates in hyperbolic rotation mode to iteratively compute the required hyperbolic sinh and cosh. The MR-HRC forms the computational core for generating the hyperbolic sinh(Zin)sinh(Z_in) and cosh(Zin)cosh(Z_in) using shift–add operations. Outputs from the HR-CORDIC stage are sent to the second stage consisting of a hyperbolic vectoring block (LV-CORDIC). This stage refines the hyperbolic results and calculates the tanh-related value from the rotated vector by using vectoring mode operations. By using LV-CORDIC, the design efficiently calculates the ratio of hyperbolic components without explicitly including any divisions or multiplications, thus maintaining a DSP-free datapath. Since there is a well-known relationship between the hyperbolic tangent and the sigmoid function, we can use the tanh output from an LV-CORDIC block to find a corresponding scaled and offset version of that output. The operation required to go from tanh to sigmoid is simply an addition operation, followed by scaling the resulting number by two constant values. Because this stage consists solely of addition and scaling by constant values, it does not have much impact on the overall hardware resource utilization. The R2-CORDIC is a traditional way of obtaining rotation using angles and coordinate points [4]. R2-CORDIC was originally created because of its easy implementation and offers good precision, but it has a slow convergence rate; thus, more iterations are needed to obtain very high precision results. The additional number of iterations means that there would be longer latencies and slower throughput. Therefore, to take advantage of both Radix-4 and Radix-2 CORDIC algorithms, a MR-HRC implementation combining Radix-4 and Radix-2 CORDIC for stable convergence is proposed. As a result, the mixed-radix approach significantly reduces the total number of iterations required to achieve a given accuracy compared to a pure radix-2 implementation. This leads to lower computational latency and improved hardware efficiency, while preserving numerical stability. Hence, the proposed mixed-radix CORDIC architecture offers an effective trade-off between convergence speed and implementation complexity, making it well-suited for high-performance and resource-constrained hardware platforms. In the following section, we have discussed the proposed modified mixed-radix hyperbolic rotation CORDIC (MR-HRC) approach to derive hyperbolic sine and cosine. 3.1 Mixed-Radix Hyperbolic Rotation Cordic(MR-HRC) In this section, we have discussed the proposed mixed-radix hyperbolic rotation CORDIC (HRC) algorithm, which combines radix-2 and radix-4 iterations to overcome the slow convergence of conventional radix-2 CORDIC. A radix-R hyperbolic rotation CORDIC (HRC) computes hyperbolic functions by applying a sequence of micro-rotations whose step sizes shrink geometrically with the iteration index. At iteration j, the elementary hyperbolic angle is typically chosen as follows: αj=tanh−1(djR−j) _j= ^-1\! (d_jR^-j ) (3) The variable djd_j in (3) indicates the digit selection function. In CORDIC, the convergence range means the set of input angles for which the iterative micro-rotations are guaranteed to reach the target angle without losing stability. The convergence range of the radix-R HRC CORDIC algorithm is defined in (4). |z0|≤∑i=1Ntanh−1(dj,maxR−j)|z_0|≤ _i=1^N ^-1\! (d_j,maxR^-j ) (4) where dj,maxd_j, represents the maximum allowable digit magnitude and N is the total number of iterations. As discussed earlier, to compute the sigmoid function over the normalized input range x∈[−1,1]x∈[-1,1], the identity σ(x)=12(1+tanh(x2))σ(x)= 12 (1+ ( x2 ) ) is employed. As a result, the required input range for the hyperbolic tangent function is reduced to Z0∈[−12,12]Z_0∈ [- 12,\, 12 ]. This restricted input range is particularly advantageous for hardware implementations, as it places the CORDIC core in a small-angle operating region, leading to improved numerical stability and reduced iteration requirements. By substituting R=2R=2 and R=4R=4 into (4), the convergence range of the radix-2 and radix-4 CORDIC can be defined as given in (5) and (6), respectively. |z0|≤∑j=1Ntanh−1(2−j)|z_0|≤ _j=1^N ^-1\! (2^-j ) (5) |z0|≤∑j=1Ntanh−1(2∗4−j)|z_0|≤ _j=1^N ^-1\! (2*4^-j ) (6) The required input convergence range for the proposed sigmoid computation is limited to ±0.5± 0.5, as established earlier through the sigmoid–tanh relationship. Based on this requirement, the R2-HRC algorithm is selected for the initial stage, with the iteration index chosen to start with j=2j=2. Using the convergence criteria defined in (5), the allowable input range for R2-HRC with the iteration index j=2j=2 can be evaluated to approximately 0.5688, which is greater than the required input range of 0.5. Hence, starting the R2-HRC iterations with j=2j=2 guarantees convergence for the required input angle. As a result, in the proposed architecture, the first stage performs R2-HRC iterations from j=2j=2 to j=9j=9. This stage ensures that the residual angle is brought down to a smaller range suitable for subsequent higher-radix rotation stages. After completing the radix-2 HRC rotation from j=2j=2 to j=9j=9, the residual angle is reduced to approximately 0.00610.0061. To continue refinement with a higher convergence speed, the next stage is initiated using R4-HRC. When the radix-4 computation starts from j=4, the corresponding admissible input range is 0.0104, which covers the residual angle produced by the R2-HRC. As a result, the transition from R2-HRC to R4-HRC satisfies the required convergence condition and does not generate an error. Therefore, the proposed design proceeds with the R4-HRC iteration in the subsequent stage. A key limitation of conventional R4-HRC is that its scale factor is not constant; it varies with both the input angle and the digit selection function djd^j. This input-dependent gain complicates hardware normalization and can introduce additional error if not compensated accurately. To avoid this issue, the proposed approach starts the R4-HRC stage at j=4j=4. When the iteration is initiated with j=4j=4, the rotation angle becomes sufficiently small such that the higher-order terms in the Taylor series expansion of the hyperbolic functions can be safely neglected without introducing any numerical error. Under this condition, the series effectively reduces to its dominant linear terms, and the associated gain converges to unity. As a result, the effective scale factor is approximately unity, so the rotation does not require an explicit scaling correction and does not introduce noticeable gain-related error. Therefore, initializing R4-HRC at j=4 enables an error-free and hardware-friendly implementation. In a radix-4 CORDIC algorithm, the digit selection function controls the amount of rotation in each iteration. Unlike radix-2 CORDIC, where the digit selection function is simple, and it depends only on the sign of the residual, radix-4 CORDIC uses a multi-valued digit set, dj∈−2,−1,0,+1,+2d^j∈\-2,-1,0,+1,+2\, which allows fast convergence. In R4-HRC, the digit selection logic is more complex than that of radix-2 CORDIC. In radix-2, the digit is determined solely by the sign of the residual angle ZjZ^j, resulting in a simple binary choice. In contrast, R4-HRC employs a multi-valued digit set, and the digit selection depends on both the sign and magnitude of the residual angle. The implementation of the complex digit selection function requires an additional comparator. In the proposed approach, the digit selection function for the R4-HRC is derived using the radix-4 SRT division. The only essential requirement imposed on the digit selection is that the magnitude of the residual angle must decrease after each iteration. The proposed digit selection ensures faster convergence compared to the conventional radix-2. In the proposed digit selection, the radix-4 SRT division is employed to derive the digit selection in each R4-HRC iteration. The scaled residual angle 4jZj4^jZ^j must be within a predefined interval bounded by a lower limit (Lj[σj])(L^j [σ^j ]) and an upper limit (Uj[σj])(U^j [σ^j ]) as defined in (7). Lj[σj]=Pj[σj]−23Pj[1] L^j[σ^j]=P^j[σ^j]- 23P^j[1] Uj[σj]=Pj[σj]+23Pj[1] U^j[σ^j]=P^j[σ^j]+ 23P^j[1] (7) where, Pj[σj]=4jtanh−1(σj4−j)P^j[σ^j]=4^j ^-1\! (σ^j4^-j ). To determine the selection criteria for the digit σj=2σ^j=2, overlapping between two intervals I1:(Lj[1],Uj[2])I^1:(L^j[1],U^j[2]) and I2:(Lj[2],Uj[2])I^2:(L^j[2],U^j[2]) is evaluated. In the proposed approach, any value within the overlapping region between the intervals I1I^1 and I2I^2 can be chosen to select the digit σjσ^j. The values selected for σjσ^j are carefully chosen to ensure that the required comparison logic for digit selection can be implemented efficiently in hardware. These values are represented in binary using 4 binary bits for simplicity and to minimize the hardware complexity as shown in (8). σj=2for 4jZj≥1.5,1for 1.5>4jZj≥0.5,0for 0.5>4jZj≥−0.5,−1for −0.5>4jZj≥−1.5,−2for −1.5>4jZj.σ^j= cases2&for 4^jZ^j≥ 1.5,\\ 1&for 1.5>4^jZ^j≥ 0.5,\\ 0&for 0.5>4^jZ^j≥-0.5,\\ -1&for -0.5>4^jZ^j≥-1.5,\\ -2&for -1.5>4^jZ^j. cases (8) This approach significantly reduces the required comparison logic, allowing for a more hardware-efficient implementation. Next, we have explained the architecture to implement the same. 3.2 Radix-2 LVC In the proposed algorithm, the R2-LVC algorithm is used to calculate the hyperbolic tangent (tanh ) from the sine (sinh ) and cosine (cosh ) values, which are computed using the MR-HRC CORDIC algorithm in the previous stage. The objective of the R2-LVC is to compute the tanh(x)=sinh(x)cosh(x) (x)= (x) (x) by performing vectoring mode operations where the R2-LVC is initialized with (X0=coshY0=sinhZ0=0) (X^0= \,Y^0= \,Z^0=0 ). After the convergence, the value of tanh \ can be calculated from the converged value of the ZNZ^N. The rotation equations for the R2-LVC are as follows: xj+1 x^j+1 =xj =x^j yj+1 y^j+1 =yj−dj⋅xj⋅2−j. =y^j-d^j· x^j· 2^-j. zj+1 z^j+1 =zj+dj⋅(2−j) =z^j+d^j·(2^-j) (9) These equations are iteratively computed until the variable yjy^j is sufficiently small, achieving convergence. The final value of tanh(x) (x) is directly obtained from the variable zjz^j. The convergence range of the R2-LVC algorithm is defined as |Y0X0|≤2 | Y_0X_0 |≤ 2. This condition ensures that the CORDIC algorithm can successfully converge to the desired result. If the ratio exceeds 2, the algorithm may fail to converge correctly. In the proposed approach, the input range for the MR-HRC algorithm is constrained to ±0.5± 0.5. The maximum value of the tangent ratio is Y0X0=tanh(0.5)≈0.52 Y_0X_0= (0.5)≈ 0.52, which is well within the convergence range of the R2-LVC algorithm. Therefore, the input range of ±0.5± 0.5 is suitable for the CORDIC algorithm, ensuring stable and accurate convergence without exceeding the required convergence bounds. 3.3 Architecture of the proposed approach The architecture of the proposed approach is structured into two main stages for efficiently computing the hyperbolic functions sinh, cosh, and tanh. The 16-bit datawidth has chosen for hardware realization as it is sufficient for most of the real-time applications. The first stage of the architecture involves a mixed-radix hyperbolic rotation CORDIC (HRC) algorithm. This stage is responsible for computing the hyperbolic sine (sinh) and hyperbolic cosine (cosh) functions. The mixed-radix approach combines radix-2 and radix-4 CORDIC iterations. Initially, the R2-HRC is applied to reduce the residual angle and get an approximate value of sinh(x) and cosh(x). The algorithm performs radix-2 CORDIC operations for iterations starting from j=2 to 9. The algorithm performs radix-4 CORDIC operations for iterations from j=4 to 7. Later, the R4-HRC further refines the results, providing more precise values of sinh(x) and cosh with faster convergence compared to using radix-2 alone. Fig.3 shows the overall architecture of the MR-HRC algorithm, whereas Fig. 4(a) and Fig. 4(b) show R2-CORDIC and R4-CORDIC architectures, respectively. Figure 3: The architecture of proposed MR-HRC algorithm Figure 4: (a)Architecture of R2-HRC algorithm(b)Architecture of R4-HRC algorithm In the proposed approach, we have implemented a pipelined architecture, where each iteration of the CORDIC algorithm has dedicated hardware, and pipeline registers are used to separate each iteration. This architecture ensures that the operations within each iteration are performed in parallel, which optimizes throughput and reduces the overall latency. Due to the pipeline architecture, the adder is the only component that determines the critical path of the R2-HRC algorithm. In the R4-HRC algorithm, the digit selection function has five different values. As a result, the critical path involves two key components: the multiplexer and the adder. The architecture of the R2-LVC algorithm is quite simple, and it is illustrated in Fig. 5. The critical datapath of the R2-LVC algorithm has only an adder. Figure 5: The architecture of the R2-LVC algorithm with adder 4 Simulation Results The proposed architecture is implemented using a 16-bit data width, which provides sufficient numerical precision for most real-time applications while keeping the hardware cost low. This choice offers a practical balance between accuracy and resource efficiency, making the design suitable for time-critical signal processing and AI/ML workloads. To evaluate its effectiveness, the proposed architecture is implemented on Xilinx Virtex-7 series FPGAs and compared with several recent state-of-the-art approaches. The comparison is carried out using standard metrics, including hardware utilization and mean absolute error. Hardware utilization reflects the efficiency of the design in terms of FPGA resources, and MAE captures the numerical accuracy of the computed results. The simulation results of the proposed architecture are compared to existing implementations using the discussed performance metrics. The proposed architecture is synthesized using Xilinx Vivado and implemented on a Virtex-7 series FPGA to ensure a fair comparison with the previous approaches. Table 1 illustrates a comparison of hardware utilization for different sigmoid implementations, where DSP usage has been converted into an equivalent logic cost for a fair comparison. In this table, Table 1: Comparison of LUT, DSP, and total hardware utilization for FPGA-Based sigmoid implementations Work LUTs DSPs DSP-Equivalent LUTs Total LUTs [7] 202 4 1540 1742 [8] 168 5 1925 2093 [10] 86 3 1155 1241 [11] 114 0 0 114 [6] 282 8 3080 3362 [1] 80 4 1540 1620 Proposed 835 0 0 835 one DSP block is treated as equivalent to 385 logic slices, and the total logic equivalent is computed by combining LUT usage with the DSP-equivalent LUTs. From the table, it can be observed that several existing approaches rely heavily on DSP blocks. Although reported hardware utilization may appear lower, the effective hardware utilization increases significantly once DSP usage is taken into account. For example, the approaches reported in [6] and [8] show total logic equivalents of 3362 and 2093 slices, respectively, primarily due to high DSP utilization. Even designs with fewer DSPs, such as [7] and [1], still have a substantial hardware utilization. In contrast, the proposed approach is implemented without DSP blocks, relying entirely on LUT-based shift-and-add operations. As a result, the total logic equivalent of the proposed design is only 835 slices, which is significantly lower than most of the compared methods. When compared with DSP-intensive implementations such as [6] and [8], the proposed architecture achieves nearly 40%40\% improvement in overall hardware utilization, highlighting its efficiency. Table 2: Comparison of mean absolute error (MAE) for different sigmoid computation methods Work Average Absolute Error [7] 1.71×10−31.71× 10^-3 [8] 1.07×10−31.07× 10^-3 [10] 4.25×10−34.25× 10^-3 [11] 5.90×10−35.90× 10^-3 [6] 2.44×10−32.44× 10^-3 [1] 1.66×10−31.66× 10^-3 Proposed 4.23×−4.23× 10^-4 Table 2 presents a comparative analysis of the mean absolute error achieved by various existing approaches and the proposed method. The mean absolute error is a widely used metric to quantify the numerical accuracy of function approximation algorithms, as it reflects the average deviation between the computed output and the ideal reference value over a large set of input samples. From the Table 2, it can be observed that several existing approaches have mean absolute errors in the range of 10−310^-3. The approached reported in [10] and [11] show relatively higher errors of 4.25×10−34.25× 10^-3 and 5.90×10−35.90× 10^-3, respectively, indicating limited approximation accuracy. Approaches such as [8] and [7] still maintain errors above 10−310^-3. The approach presented in [1] achieves a moderate improvement; however, its error remains significantly higher than that of the proposed design. In contrast, the proposed approach achieves a mean absolute error of only 4.23×10−44.23× 10^-4, which is substantially lower than all the compared methods. This represents a significant improvement in numerical accuracy, demonstrating the effectiveness of the proposed mixed-radix CORDIC-based formulation and the careful selection of iteration ranges. 5 Conclusion We have presented a hardware-efficient FPGA implementation of the sigmoid activation function based on a mixed-radix hyperbolic rotation CORDIC architecture in this paper. We have used the mathematical relationship between the sigmoid and hyperbolic tangent functions; the proposed approach effectively converts the expensive sigmoid computation into a sequence of CORDIC-based hyperbolic rotation and division operations followed by simple scaling and offset adjustments. We have normalized the input range to ±1± 1, which further reduces the convergence range of the MR-HRC algorithm. The main objective of this work is to design a modified mixed-radix hyperbolic rotation CORDIC (MR-HRC) algorithm that combines radix-2 and radix-4 iterations. The radix-2 stage guarantees the initial convergence for the required input range. The input X0X^0 of the algorithm is initialised with 1Kh 1K_h so that the scale factor generated by radix-2 CORDIC can be compensated without any additional hardware. Later, the radix-4 stage makes convergence faster by producing two bits of result in each iteration. The subsequent radix-2 linear vectoring CORDIC (R2-LVC) stage efficiently computes the hyperbolic tangent using only shift-and-add operations, resulting in a DSP-free datapath. The proposed architecture is fully pipelined and implemented using a 16-bit fixed-point representation, making it well-suited for real-time and resource-constrained applications. Implementation on an Xilinx Virtex-7 FPGA demonstrates that the design achieves a total logic equivalent of only 835 slices with zero DSP usage. In addition, the achieved mean absolute error of 4.23×10−44.23× 10^-4 confirms the high numerical accuracy of the proposed method. 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