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Hardware Design and Security in the Era of Chiplets and LLMs
Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz, Ramesh Karri
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Abstract:The semiconductor industry is undergoing a dual revolution: the shift toward heterogeneous 2.5D chiplet systems and the integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) flows. While these paradigms offer unprecedented benefits in yield, modularity, design productivity, etc., they radically expand the hardware attack surface. This paper provides a unified analysis of these frontiers, ranging from attacks on chiplet systems (including hardware stacks for LLM acceleration) across architectural, logical, and physical levels, to various exploits against LLM-driven EDA pipelines. To secure chiplet systems, we review a powerful defense approach that leverages 2.5D split manufacturing and active interposers for physically isolated Root of Trust (RoT) architectures. To secure LLM-driven EDA pipelines, we first identify native threats and then review state-of-the-art defense techniques. Finally, we discuss how LLM systems can advance hardware security efforts for modern systems, including chiplets.
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Hardware Design and Security in the Era of Chiplets and LLMs Johann Knechtel Ozgur Sinanoglu Paul V. Gratz Ramesh Karri Abstract The semiconductor industry is undergoing a dual revolution: the shift toward heterogeneous 2.5D chiplet systems and the integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) flows. While these paradigms offer unprecedented benefits in yield, modularity, design productivity, etc., they radically expand the hardware attack surface. This paper provides a unified analysis of these frontiers, ranging from attacks on chiplet systems (including hardware stacks for LLM acceleration) across architectural, logical, and physical levels, to various exploits against LLM-driven EDA pipelines. To secure chiplet systems, we review a powerful defense approach that leverages 2.5D split manufacturing and active interposers for physically isolated Root of Trust (RoT) architectures. To secure LLM-driven EDA pipelines, we first identify native threats and then review state-of-the-art defense techniques. Finally, we discuss how LLM systems can advance hardware security efforts for modern systems, including chiplets. I Introduction The semiconductor industry is rapidly transitioning from monolithic Systems-on-Chips (SoCs) toward high-density 2.5D chiplet-based architectures [38, 4, 40]. This paradigm enables a modular “plug-and-play” ecosystem where third-party chiplets are manufactured separately and integrated onto a silicon interposer. However, the reliance on multi-vendor supply chains introduces significant trust gaps, as individual chiplets may originate from untrusted foundries or design houses, threatening the overall system’s integrity [35, 8]. These chiplets must share a common interconnect fabric and memory space, making system-level communication a highly vulnerable surface [8, 54]. Such threats apply to any chiplet system, including heterogeneous accelerator architectures for deployment of large language models (LLMs) [74, 44, 11]. Independently, LLMs for electronic design automation (EDA) tooling have significantly accelerated hardware-design workflows [62, 29, 71]. For example, transformer-based architectures automate hardware description language (HDL) coding and formal verification [55, 6]. However, this automation also introduces threats for hardware design, including leakage of design IP, backdoor poisoning, and data/benchmark contamination [65, 33, 64]. Simultaneously, LLM frameworks become capable of assisting security measures, e.g., automatic generation of security assertions [27]. Protecting this modern and complex landscape of chiplet systems and wide-scale use of LLMs requires new solutions on multiple fronts. For the hardware, a fundamental shift from chip-level security to system-level architectures built on physically isolated Roots of Trust is required. For LLM operation, orchestrating agents within trusted boundaries for hardware, software, and data operation is required. Crucially, there is a lack of cross-domain understanding bridging these paradigms. While attackers are poised to exploit fuzzy boundaries when multi-vendor fabrics interface with sensitive acceleration hardware, current research fails to leverage trustworthy LLMs to secure complex chiplet systems and vice versa. Here, we review the state-of-the-art in chiplet security, focusing on interposer-based defenses. We also unravel the dynamics of LLM-native EDA flows and their promises for hardware design, alongside related risks and emerging defenses. Finally, we are charting a path toward synergetic and secure operation of chiplet systems and LLM pipelines. I Background I-A Chiplet Systems 2.5D integration uses interposer to interconnect separately manufactured chiplets, reducing time-to-market and improving yield compared to monolithic SoCs [58, 37].111Aside from 2.5D integration, 3D IC technologies like through-silicon via (TSV) stacked logic, face-to-face bonding, and monolithic 3D integration have gained significant momentum as well. See also [30] for such technologies in general and for related hardware-security aspects in particular. While current systems are mostly homogeneous and cache-coherent, the trend toward heterogeneity allows designers to integrate different commodity chiplets, each designed and manufactured for an optimized process [37, 58]. Interposers are classified as passive (wiring only) or active (wiring and logic) [26]. Active interposers with network-on-chip (NoC) infrastructure separate the interposer’s fabric from chiplet interconnects, enabling cross-optimized networking topologies and improved testability [73]. I-B LLM-Driven Hardware Design: Challenges and Solutions I-B1 From Prompting to Optimization and Reasoning Early works often yielded flawed code, leading to feedback-driven agents like AutoChip [6] that autonomously correct compiler errors. [18] treats register-transfer level (RTL) code generation as a state-space search with backtracking. Frameworks such as VeriThoughts [75] utilize reasoning models like DeepSeek-R1 to generate Chain-of-Thought traces, employing formal verification to mitigate hallucinations. I-B2 Representation and Synthesis Bottlenecks Intermediate representations constrain LLM coding performance. While sufficient Verilog data allows for high pass rates, High-Level Synthesis (HLS-C) suffers from an “accessibility-competence paradox” due to data scarcity [20]. To bridge this software-to-hardware gap, frameworks like C2HLSC [14] utilize LLMs to refactor standard C into synthesizable HLS-C, while automated pipelines inject pragmas based on synthesis reports [28]. Beyond text, enhancing structural awareness via graph representations (RTL++ [3]) or fine-tuning models to output conjunctive normal-form clauses (Veritas [48]) ensures correct-by-construction synthesis through propositional logic. I-B3 Assertions and Testbenches LLMs can generate SystemVerilog Assertions (SVA) [27], though grounding them in RTL semantics remains challenging [57]. Deterministic decoding and specialized retrieval-augmented generation (RAG) frameworks [69] improve SVA accuracy. Coverage-driven agents can iteratively expand testbenches to achieve near-total transition coverage for complex state machines [5]. I-B4 Model Orchestration, Configuration, and Evaluation VeriDispatcher [61] reduces API costs by 40% by routing tasks to models based on predicted difficulty. Evaluation via the Hardware Quality Index [21] has identified failure modes like complexity timeouts in frontier models. Crucially, inference-time configuration can impact pass rates by over 25%; since optimal hyperparameters do not transfer across benchmarks, task-aware calibration is more vital than model size [52]. I Threats for Chiplet Systems Multi-vendor chiplet systems introduce significant risks once chiplet design and fabrication are being outsourced, compromising the trust of system integration [35, 8]. Traditional security primitives, such as ARM TrustZone or Intel SGX, fail to extend protection across chiplet boundaries, leaving the system vulnerable [35]. I-A Architectural and Logical Attacks The shared interconnect and memory space form the primary vector for architectural exploits [8, 54]. Similar to NoC vulnerabilities in concept [9], yet different in execution, 2.5D systems are prone to inter-chiplet communication attacks like snooping and spoofing [35, 8]. The underlying threat for these attacks are malicious chiplets undermining the security of other chiplets when integrated into the same 2.5D system. In systems with cache coherence (C), memory consistency is maintained across chiplets through low-level communication. However, C protocols operate transparently to operating system (OS)-level permissions, allowing Trojans in C controllers to bypass page-table protections and manipulate OS-restricted memory regions by injecting malicious, unverified coherence responses [8]. Protocols like MOESI Hammer [15], which rely on broadcast traffic, are susceptible to multi-stage Forging Attacks [8]. This exploit requires no address space ownership, leaving the global C mechanism and the victim chiplet unaware of the compromise. Shared C fabrics also expose chiplets to microarchitectural threats: attackers can infer memory access patterns through NoC contention and latency without issuing unauthorized requests [7]. Trojans may also leverage speculative execution by issuing out-of-bounds prefetch requests that utilize C protocol state changes to reveal information about a victim chiplet’s working set [8]. While applicable to any 2.5D system, such threats are particularly concerning for heterogeneous LLM hardware stacks, with general-purpose CPUs, dedicated accelerator cores, and shared memories arranged across different chiplets [74, 44, 11]. For example, LLM inference demands large-scale memory transfers for weights and activations; the resulting multi-chiplet traffic exhibits highly predictable patterns. Malicious third-party chiplets could exploit NoC and C vulnerabilities discussed above, aiming to reconstruct model architectures or steal proprietary weights. The current literature scrutinizes LLM stacks on monolithic SoCs [67, 22]; structural vulnerabilities of multi-vendor chiplet systems executing distributed acceleration remain a critical and unaddressed security gap. I-B Physical Attacks Side-channel attacks (SCAs) exploit physical leakage such as power consumption, timing variations, and speculative cache states to infer sensitive data [76, 31]. Fault-injection attacks (FIAs) use techniques like laser and electromagnetic pulses [16] to fix/glitch specific signals, e.g., to assist SCAs or to disrupt security features. There are also indirect FIA methods like memory hammering (RowHammer) or exploiting dynamic voltage and frequency scaling (DVFS) [56]. Using failure-analysis equipment like invasive ion-beam milling or semi-invasive electro-optical probing, adversaries can execute read-out attacks on logic and memory [59]. Recent studies have demonstrated physical attacks also on LLM systems [25, 17]. While most if not all of these studies are limited to LLM software stacks operating on regular SoCs, future attacks on chiplet-based LLM systems are equally realistic and concerning. IV Securing Chiplet Systems Most 2.5D Root of Trust (RoT) proposals utilize a centralized chiplet for authentication and security management [32]. However, untrusted manufacturing can compromise that RoT, and its limited visibility allows malicious chiplets or NoC-level Trojans to bypass defenses [9]. Furthermore, traditional NoC security techniques [9] assume a single trusted designer; in multi-vendor systems, the interconnect itself may be compromised, necessitating security monitors that are physically isolated from the NoC fabric. IV-A 2.5D RoT: Physical and Architectural Foundations Split manufacturing, traditionally proposed for 2D and 3D ICs [43, 42], can also secure 2.5D integration, e.g., against IP piracy and Trojans [70, 30]. By concealing system-level routing within interposers, designers hide the full netlist from chiplet foundries, obscuring IP context and potential attack targets [70, 30, 42]. Importantly, this concept can also be used for physical separation of trusted security features and untrusted commodity chiplets as described next. Active interposers can incorporate sensitive logic such as secured NoC routers, enabling them to function as a physically isolated 2.5D RoT [41, 35]. Using mature nodes, active interposers can be fabricated in trusted on-shore facilities [41]. The 2.5D RoT enforces strict physical separation: untrusted commodity chiplets must rely entirely on the interposer’s fabric for communication, rendering attacks like spoofing impossible, as network interfaces reside within the trusted interposer logic [8, 35]. Other attacks can be mitigated by runtime monitoring as discussed next. IV-B Runtime Monitors: Microarchitecture and Operation A 2.5D RoT built from an active interposer can embed Transaction Monitors (TRANSMONs) as hardware-level shims between untrusted chiplets and the interposer’s NoC fabric [35]. Such TRANSMONs provide multi-layer protection: they enforce access control via core ID and policy checks, and data-masking hinders “shadow writes” against leakage of cryptographic assets etc. Managed by an on-interposer secure core, these units implement a deny-by-default stance. For memory integrity, TRANSMONs facilitate parallel ECC/CRC verification by offloading metadata to trusted memory chiplets, neutralizing read-latency overheads [35]. Crucially, as TRANSMONs are C-agnostic, Coherence Message Checkers (CMCs) can be integrated into the NoC ingress to prevent protocol-level exploits [8]. They validate coherence flits against secure OS-managed permissions in two variants: CMC-1 sits at the chiplet-NoC boundary to intercept malicious incoming flits, while CMC-2 is integrated with memory controllers to neutralize snooping. In broadcast-heavy protocols like MOESI Hammer, CMC-2 dynamically transforms broadcasts into targeted unicasts or NACKs, effectively masking transaction existence from unauthorized cores with minimal pipeline latency (1–2 stages) [8]. Beyond mitigating architectural and logical attacks, the 2.5D RoT interposer fabric can provide trusted integration of sensors and other hardware security features against physical attacks. This is especially promising for LLM hardware stacks that are composed of heterogeneous chiplets from multiple vendors, where individual chiplets may offer limited built-in security features [74, 44, 11]. Furthermore, 3D ICs can provide comprehensive shielding structures across metal layers and TSVs, mitigating a wide range of physical attacks directly by construction [30, 39]. IV-C Physical Design and Performance Impact Active interposers fundamentally improve power and signal integrity [41]: embedding integrated voltage regulators (IVRs) helps to minimize the distance to power-demanding logic, reducing the maximum IR-drop by 73.7%, and embedded repeaters mitigate signal distortion by eliminating long, unbuffered wires [41]. An active 2.5D design can reduce the total system silicon footprint by 18.5% because the NoC and IVRs are removed from the surface-level chiplets [41]. At the same time, the interposer maintains a low utilization rate of 2.68%, avoiding concerns for yield loss of interposers [41]. The performance impact for CMC-driven runtime monitoring is ≈ 4% on average, while total system power is reduced by 3.2% compared to unsecured baselines [35, 8, 41]. V LLM-Driven EDA Flows: Threats and Defenses As design houses increasingly adopt LLM-driven EDA workflows, establishing trust in model training, operation, and EDA tool integration becomes critical. Prominent threats and state-of-the-art defenses are discussed next. V-1 Backdoor Attacks RTL-Breaker [33] demonstrates that fine-tuning on public RTL repositories exposes models to data poisoning. Attackers can embed rare keywords as activation triggers that cause the backdoored model to generate Trojans or sub-optimal circuitry while maintaining valid syntax, allowing these modifications to evade standard functional checks. SafeTune [46] addresses poisoning through offline dataset sanitization with an online inference guard, lowering the attack success rate down to 33%. Semantic Consensus Decoding (SCD) [72] exploits the locality bias, assuming adversaries embed triggers within non-functional modifiers. At inference time, core functional requirements are extracted from the user prompt; significant divergences in full vs extracted specification trigger the framework to fall back to clean functional generation, reducing the observed attack rate to near 0%. V-2 Data Contamination This leaks benchmark test sets into training data, artificially inflating evaluation scores through memorization. VeriContaminated [64] utilizes Min-K% probability and Contamination Detection via Distribution (CDD) metrics to reveal near-100% contamination of standard benchmarks like VerilogEval across recent commercial models. Mitigating this threat requires a shift to dynamic benchmarking [10] or model sanitization [63]. Dynamic benchmarking establishes time-variant testing corpora that shift along model timestamps and/or utilizes rule-/template-based problem generation to mitigate collision rates [10]. Alternatively, when data exposure has already occurred, model sanitization can be pursued post-hoc via machine unlearning frameworks like SALAD [63]. This framework leverages tailored loss primitives like gradient difference or Negative Preference Optimization (SimNPO) to sever the model’s memory of contaminated test data (and malicious backdoors and sensitive IP) while retaining general RTL coding fidelity [63]. V-3 Safety Misalignment Prompt injection (PI) poses a fundamental risk to LLM systems [24]. A related concern is that established safety alignment lacks hardware-domain understanding. HarmChip [60], a recent safety benchmarking effort covering 16 domains and 120 threats, revealed that keyword-sensitive guardrails indiscriminately block legitimate engineering tasks, while adversaries can bypass the same guardrails using semantic disguise, e.g., by framing attacks as engineering change order (ECO) optimizations. Defending against PI attacks demands structured runtime validation frameworks that treat untrusted instructions separately from system prompts [24]. These frameworks combine embedding-based classification layers with strict structural parsing, neutralizing embedded trigger sequences before they interface with core execution layers. To address the safety-alignment gap highlighted by HarmChip, frameworks must transcend general-purpose defense tuning by embedding domain-specific engineering logic directly into the model’s safety boundaries [60]. By executing multi-task optimization using dual-purpose adversarial pairs, models can be calibrated via preference optimization algorithms (such as DPO and SimNPO) to evaluate the true underlying intent. V-4 IP Leakage While promising for design quality, fine-tuning on in-house codes risks leaking the underlying IP. VeriLeaky [65] demonstrated that, by providing only few structural hints like interface declarations, models can be coerced into flawlessly regenerating sensitive IP. VeriLeaky also showed that logic locking can be applied before fine-tuning to reduce leakage, but it comes at the cost of training utility [65]. As indicated, SALAD [63] resolves this and other threats via machine unlearning. CircuitGuard [34] proposes a dual-stream mechanism: pre-training sanitization and vocabulary masking. Applying adaptive token-level noise masks during gradient descent optimization, CircuitGuard mitigates both verbatim and behavioral replication of proprietary IP without modifications to the baseline architecture. VI LLMs for Hardware Security LLMs are also increasingly utilized to implement and verify hardware security across various settings. VI-1 IP Protection Logic locking utilizes key-dependent gates to protect design IP. GLLaMoR [50] speeds up traditional topological analysis by converting netlists to lock into adjacency lists for multi-hop graph reasoning in LLMs. LockForge [51] devises a multi-agent setup (Coder, Judge, Examiner) to parse academic PDFs and validate locking implementations via similarity scoring. Similarly, the framework in [23] couples RAG with SAT-based iterative refinement for locking. For IP redaction, ARIANNA [13] automates FPGA design-space exploration (DSE) using module clustering and branch-and-bound algorithms, cutting area overhead by 3.3×. VI-2 SCA Mitigation and Cryptography Accelerators Traditional pre-silicon SCA assessment requires exhaustive design and power simulation runs. NetlistWhisperer [49] uses an ensemble of fine-tuned LLMs to predict gate-level leakage bounds and to secure netlist implementations via Domain-Oriented Masking (DOM). For Post-Quantum Cryptography (PQC), LLM4PQC [45] proposes an agentic workflow to isolate critical kernels, refactor dynamic arrays and other C constructs from reference codes (to resolve HLS obstacles), and run DSE for FPGA implementation. The framework has been extended to generate SCA-resilient accelerators [36]. VI-3 Trojan Detection Prior art utilizes graph neural networks (GNNs) operating on gate-level netlists directly or on graph representations of RTL [19]; both views discard textual context from the original HDL, undermining detection accuracy. In contrast, TrojanLoC [68] Trained on the TrojanInS dataset, it uses devises an RTL-adapted transformer to extract token- and line-level embeddings, achieving a 99% F1-score for module-level detection and precise payload localization via lightweight classifiers. VI-4 Red-Teaming Evaluating security defenses requires adversarial red-teaming to uncover blind spots. NetDeTox [66] critiques GNN piracy detectors using a hybrid framework; a reinforcement learning (RL) agent screens high-leverage netlist restructuring options, and an LLM agent plans gate transformations, evading detection in 90% of cases, while optimizing area. TrojanGYM [53] implements an attack-defense agentic loop, restructuring netlist properties until generated Trojans successfully evade GNN classifiers at an 83% rate. VI-5 Bug Detection and Code Analysis Common Weakness Enumerations (CWEs) often depend on microarchitectural context, making simple pattern-matching ineffective. VeriCWEty [47] addresses this through a Verilog-tuned decoder that extracts module- and line-level embeddings; paired with an ensemble-labeled dataset, the classifier achieves 89% precision in identifying vulnerabilities and 96% localization accuracy. LASHED [1] pairs static analysis with LLMs to contextualize errors and eliminate false positives, while MARVEL [12] employs a hierarchical multi-agent setup (Linter, CWE, and RAG executors). Finally, FLAG [2] enables test-free fault localization by calculating token logprobs and semantic embedding distances directly from source code. VI-6 Gap for Securing Chiplet Systems While LLMs have been used successfully for securing hardware in general, their dedicated application to securing 2.5D/3D systems is missing. Current LLM setups lack semantic awareness of system-level interconnect fabrics, multi-vendor trust boundaries, and active interposer configurations. Without domain-aware agents capable of synthesizing system-wide security constraints and mapping them to physical enforcement primitives, identifying hidden flaws in complex 2.5D/3D systems remains a severe bottleneck, leaving a window of vulnerabilities before human designers can deploy patches. VII Conclusion and Outlook The convergence of 2.5D chiplet systems and LLM-accelerated EDA pipelines necessitates a dual paradigm shift toward system-level, secure-by-construction architectures on the one hand and orchestrated multi-agent loops operating within rigorously verified boundaries on the other hand. Looking beyond the significant advances in both domains, we call for a more synergetic ecosystem: deploying trusted, aligned LLM frameworks to verify and secure chiplet systems, while utilizing 2.5D-anchored RoT architectures to accelerate and safeguard multi-vendor LLM deployment. Accordingly, future research may utilize frontier models to bridge the gap between high-level security requirements and low-level physical enforcement mechanisms, e.g., for automated generation of access policies for TRANSMONs and CMCs directly from architectural descriptions and OS-initiated permissions. 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