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Syn2Logic: End-to-End Neuromorphic Design Automation
Artur Podobas
Intelligence
Status: succeeded | Model: Gemma-4-26B-A4B | Prompt: intel-v1 | Confidence: 90%
Last extracted: 8/27/2026, 5:27:49 AM
Summary
The paper introduces Syn2Logic, a prototype framework for electronic Neuromorphic Design Automation (eNDA) that bridges computational neuroscience modeling with traditional Electronic Design Automation (EDA). Syn2Logic utilizes a custom domain-specific language (DSL) to allow neuroscientists to model neural behavior without writing hardware description language (HDL) code, automatically compiling these models into synthesizable RTL for FPGAs and ASICs. The framework demonstrates significant performance improvements in three key applications: accelerating C. elegans connectome simulation, solving Sudoku puzzles faster than classical solvers, and achieving high energy efficiency on the MNIST dataset.
Entities (10)
Relation Signals (8)
Syn2Logic → implements → eNDA
confidence 95% · Syn2Logic is a prototype implementation of the eNDA methodology concepts.
Syn2Logic → uses → DSL
confidence 92% · Syn2Logic is an entire eNDA framework, that allows neuroscientists to model neural behavior using a custom DSL
Syn2Logic → compilesto → RTL
confidence 90% · compiler that takes the same model description down to synthesizable RTL hardware.
Syn2Logic → accelerates → C. elegans
confidence 88% · generate what we believe is the fastest C. elegans accelerator that runs significantly faster than state-of-the-art simulators
Syn2Logic → classifies → MNIST
confidence 85% · create a 5.6 million FPS/Watt accelerator... on the MNIST dataset.
Syn2Logic → solves → Sudoku
confidence 85% · create (to the best of our knowledge) the fastest, most generic neuromorphic sudoku solver
Syn2Logic → outperforms → CP-SAT
confidence 80% · outperforms CP-SAT and SCIP on TOP1465 puzzles
Syn2Logic → outperforms → SCIP
confidence 80% · outperforms CP-SAT and SCIP on TOP1465 puzzles
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Abstract
Abstract:In this work, we propose a view on electronic Neuromorphic Design Automation (eNDA), which we see as a design automation flow that bridges computational neuroscience modeling with traditional Electronic Design Automation (EDA) flow. We introduce the term, give examples of how it can be implemented, and design a prototype implementation: Syn2Logic. Syn2Logic is an entire eNDA framework, that allows neuroscientists to model neural behavior using a custom DSL and a compiler that takes the same model description down to synthesizable RTL hardware. We end the paper by applying the eNDA-flow through Syn2Logic to show how to -- without writing a single line of hardware description language (HDL) code-- (i) generate what we believe is the fastest C. elegans accelerator that runs significantly faster than state-of-the-art simulators, (ii) create (to the best of our knowledge) the fastest, most generic neuromorphic sudoku solver that outperforms CP-SAT and SCIP on TOP1465 puzzles, and (iii) create a 5.6 million FPS/Watt accelerator on a tiny FPGA that outperforms existing neuromorphic architectures in terms of speed and energy-efficiency on the MNIST dataset.
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- Source: https://arxiv.org/abs/2608.25536v1
- Canonical: https://arxiv.org/abs/2608.25536v1
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Syn2Logic End-to-End Neuromorphic Design Automation Artur Podobas Department of Computing and Learning Systems, KTH Royal Institute of Technology, Brinellvägen 8, 100 44, Stockholm Sweden. Contributing authors: podobas@kth.se; Abstract The termination of Dennard’s scaling and the end of Moore’s law are forcing researchers and computer specialists to consider systems other than classical computers. Among these emerging post-Moore systems are neuromorphic architectures— systems built to resemble and replicate the fantastic computing power of the biological brain. Neuromorphic systems are emerging as a strong candidate to solve problems faster or more energy-eciently within elds such as computational neuroscience, optimization theory, or articial intelligence/machine learning. Prior work has demonstrated prototypes that outperform classical systems by nearly three orders of magnitude on certain problems, and much of the success of neuromorphic engineering builds on advances within computational neuroscience. In this work, we propose a view on electronic Neuromorphic Design Automation (eNDA), which we see as a design automation ow that bridges computational neuroscience modeling with traditional Electronic Design Automation (EDA) ow. We introduce the term, give examples of how it can be implemented, and design a prototype implementation: Syn2Logic. Syn2Logic is an entireeNDAframework, from language-to-RTL, that allows neuroscientists to model neural behavior using a custom DSL and a compiler that takes the same model description down to synthesizable RTL hardware. We end the paper by applying theeNDA-ow through Syn2Logic to show how to — without writing a single line of hardware description language (HDL) code—(i)generate what we believe is the fastestC. elegans accelerator that runs signicantly faster than state-of-the-art simulators,(i)create (to the best of our knowledge) the fastest, most generic neuromorphic sudoku solver that outperforms CP-SAT and SCIP, and(i)create a 5.6 million FPS/Watt accelerator on a tiny FPGA that outperforms existing neuromorphic architectures in terms of speed and energy-eciency on the MNIST dataset. Keywords:Neuromorphic Design Automation, Computational Neuroscience, Post-Moore 1 Introduction With the end of Dennard’s scaling [1] and the impending end of Moore’s law [2], the computer science community is actively pursuing alternative forms of computing to continue the performance scaling [3] we have grown accustomed to. Many of these alternative forms of computing are so-called post-Moore technologies, ranging from analog computers to quantum computers. However, none is perhaps as salient as that called neuromorphic computing. Neuromorphic computing [4] is a computing paradigm that involves mapping the algorithm to a set of biologically inspired neurons and synapses, whose conguration solves computationally demanding problems. Neurons can be viewed as actors that sparsely communicate with each other, while synapses are the strength of information between neurons. Neuromorphic computing is most often (but not always) implemented using Spiking Neural Networks (SNNs) [ 5]– the third generation neural network models. Unlike an imperative application running on a classical (Von-Neumann) system, neuromorphic systems can be both faster and more energy-ecient. Examples of the types of problems solved using neuromorphic computing include articial intelligence (AI) [6–8], computational neuroscience [9,10], graph traversal/processing [11], and combinatorial optimization problems [12–14]. 1 Neuromorphic computing is often performed on a neuromorphic architecture [15,16], which is a specialized architecture – either digital-, analog-, or mixed-signal – that emulates neurons and synapses in silico, exploiting the large amount of parallelism, event-driven nature, and sparseness that neuromorphic computing oers. To be called a neuromorphic architecture, it must primarily support [17](i)compute using neurons and synapses, and(i)communication is performed with spikes (action potentials); other traits such as being massively parallel, co-locating memory and computation, and being event-driven are important implementation design-decisions [16]. Some notable neuromorphic architectures include SpiNNaker I and I [18,19], IBM TrueNorth [20], Intel Loihi [21], and BrainScaleS [22] 1 . Neuromorphic computing algorithmsrequireneuromorphic architecture, as these algorithms do not map well to classical imperative computers. For example 2 ,(i)simulating onemm 2 cortical sheet [25] is2.7xfaster and 18.8x more energy-ecient on a neuromorphic Field-Programmable Gate Array (FPGA) than using an Nvidia V100 GPU [26],(i) solving a Least Absolute Shrinkage and Selection Operator (LASSO) optimization on Intel Loihi [23] is ve orders of magnitude faster than on a traditional Intel CPU, and(i)Deep-Learning (DL) inference on CIFAR10 [27] on IBM TrueNorth is 90x more energy-ecient than NVIDIA Titan X. Hence, to advance neuromorphic computing research and adaptability, there is a fundamental need for high-performance neuromorphic architectures. In this paper, we propose what futureelectronicNeuromorphicDesignAutomation (eNDA) should be– a concept that extends the concept of electronic design automation (EDA)andcomputational neuroscience to allow push- button generation of custom neuromorphic architectures from rst-principle descriptions of neural dynamics targeting Field-Programmable Gate Arrays (FPGAs) and Application-Specic Integrated Circuits (ASICs). Additionally, we introduce Syn2Logic, which is a prototype implementation of theeNDAmethodology concepts, including a custom, multi-paradigm, domain-specic language (DSL) that combines concepts of hardware description languages (e.g. VHDL and Verilog) with classical neural modeling language (e.g., NestML [28]) while also integrating templatized multiple dispatch-like (similar to Julia [29]) and methodologies for building neuromorphic neural networks. Finally, we introduce a class-4 [16] capable Syn2Logic backend, which we use to performeNDAexploration of neuron- and synapse-model and their networks, some of which have never been mapped down to silicon. We end the paper by pushing the state-of-the-art in neuromorphic systems in three ways:(a)we show how the proposedeNDA-ow can be used to create an accelerator that simulates theCaenorhabditis elegans(a nematode commonly used as a model organism) level-A (leaky integrate-and-re) connectome faster than any other methodologies, reaching between 392x-143,971x faster simulation speed than state-of-the-art simulators running on server-class systems,(b)we develop a neural optimization solver for Sudoku, solving a 46-puzzle benchmark (including the notoriously hard AI escargot) up to 96.2x (ASIC estimates) and 28x (FPGA) faster than modern solvers such as SCIP [30] and CP-SAT [31], generalizes to other puzzles (including the famous top1465 puzzle set) and – for a few puzzles – is able to compete with tdoku[32]; the world’s fastest, hand-written, SIMD-based Sudoku solver, and(c)we use the proposedeNDA-ow to show how to design a MNIST-classier that – to the best of our knowledge – is the currently fastest SNN MNIST classier in existence, reaching 5.6 million frames-per-second/Watt and 1.72 million frames-per-second, outperforming existing FPGA SNN accelerators by several orders of magnitude and being faster than ASICs such as Intel Loihi and IBM TrueNorth using a tiny FPGA (Altera MAX10) from 2014. 2 Neuromorphic Design Automation Today, computational neuroscientists, neuromorphic algorithm developers, and neuromorphic hardware designers operate in (mostly) two very isolated environments (Figure1). Computational neuroscientists adopt a ow (Figure1:a) where algorithms and neuron- and synapse-dynamics are described using the very foundational mathematical models that govern them in computer simulator frameworks such as NEST [33], Brian2 [34], or GeNN [35], where the software is also responsible for executing the described models on some classical computer hardware, such as central processing units (CPUs), graphical processing units (GPUs), or the odd neuromorphic architecture (e.g., SpiNNaker [18]) that might support the model. Neuromorphic algorithm developers and end-users, similarly, leverage frameworks such as snnTorch [36] and SpikingJelly [37] for creating neural networks solving dierent problems. The observation to be made here is that these domain- and application- experts rely on general-purpose hardware for running their experiments– hardware that we know [23,24,26,38] is not a good match for the event-driven and extremely parallel nature of said models. There is also a surge in programming frameworks such as Lava [39], NxTF [40], PyNN [41], Nengo [42], and Fugu [43] that attempt to bridge programming and mapping neuromorphic devices from a higher abstraction level to simplify the use of these devices. Proposals such as Neuromorphic Intermediate Representation (NIR) [44] provide an intermediate language that facilitates backend mapping to both neuromorphic and classical systems. A hardware designer, on the other hand, works with a dierent ow (Figure1:b), where they decide – often what iseasy to implement rather than what is new – on a particular neuron- and synapse-model and make several hardware-friendly 1 For an exhaustive list, we redirect the reader to two excellent surveys on the topic [ 15,16] 2 For a more exhaustive list of opportunities, see the excellent summaries by Davies et al. [ 23] and Schuman et al. [17,24]. 2 FPGA bitstream ASIC GDSII (c) NeuromorphicDesign Automation (eNDA) Lexical Analysis Language Parsing Abstract Syntax Tree Semantic Analysis Model Analysis High-Level Optimizations Hardware Optimizations Neuromorphic Generation (a) Software flow (b) Hardware flow Hardware designer (old) Manuallywrites neuromorphicsystems. Computational neuroscientists or end-user Neural Dynamics SNN Simulator RTL Design Simulation & Validation NEST, Brian2, Neuron, GENN, etc. Logic Synthesis Place & Route Board Support Package ExistingEDA ProposedNDA Network Analysis Software Flow Hardware designer (eNDA) Describeshow neuromorphic systems shouldbe generated. Fig. 1: (c)eNDAis the missing link between traditional neuroscientic algorithm development (a) and the well-known electronic design automation (EDA) ow that hardware designers use for ASIC/FPGA creation (b), allowing push- button generation of neuromorphic systems supporting state-of-the-art algorithms and increased technology transfer in the neuromorphic domain.eNDAshifts the role of the hardware designers from recurrent manual and laborious hardware design to non-recurrent decision making inside the framework, focusing onhowa neuromorphic platform should be implemented. optimizations to the model that may or may not be appropriate for the experiments performed by the computational neuroscientists. The nal design is described using hardware description languages (VHDL, Verilog, or alternatives) and manually (often iteratively) mapped down towards either FPGA or ASIC using existing Electronic Design Automation (EDA) tools, resulting in an FPGA bitstream or ASIC GDSII output. There are two observations to be made here:(i) the entire process is very labor-intensive, and would have to be repeated for changes made to the chosen models with no obvious ways of design-space exploration (DSE) and automation,(i)the ow is often detached from the models and expectations that computational neuroscientists and end users actually need 3 . A prime example of the second observation is that it took more than a decade for Spike-Timing-Dependent Plasticity (STDP) [45] to make it into hardware since its discovery in 1997, and the model organismC. elegans[46], our largest fully mapped connectome (prior to the recently released Drosophila melanogaster [47]) has not been fully accelerated in hardware. And while there are several excellent SNN-to-FPGA/ASIC generation frameworks (see our recent survey on the topic [16]), they createxed-functionalityneuromorphic hardware based on architecture templates with xed topology, parameters, and neuron/synapse model (often one or several IF/LIF variants), and not oering the freedom of model/network expressivity that might be needed to develop new theories, use-cases, advanced models 4 , and networks. Examples of such excellent work include DeepFire2 (S-CNN) [48], RANC [49] (parameterizable overlay), Spiker+ (LIF-based generator) [50], QUANTIENC [51], and HLS4ML [52], (that uses High-Level Synthesis). However, to the best of our knowledge, no prior work combines(i)a hardware-oriented exible domain-specic language for arbitrary models (from simple LIF to complex Hodgkin-Huxley and beyond), synapses, and plasticity dynamics,(i)automated precision/bandwidth/timestep design-space exploration, and(i)direct synthesis to both FPGA bitstreams and ASIC layouts. We propose the electronic Neuromorphic Design Automation (eNDA) methodology, shown in Figure1:c, which bridges algorithmic and neuroscientic descriptions with EDA tool-ow, allowing application, models, and hardware designers to operate within one umbrella. AneNDA-ow takes as input the domain-specic model of a neural system as specied by a domain expert and automatically – through a series of complex transformations – transforms this high-level abstraction down to a custom and specialized neuromorphic platform, where EDA-ow takes it down to hardware.eNDAchanges the hardware designer’s role signicantly. Rather than relying on insuciently informed 3 Worth mentioning is the Intel Loihi program that engaged the community in providing feedback for their platform in between generations. 4 As the reader soon will see with our Sudoku-solver, even heavy modications to the neural dynamics is sometimes needed to solve problems better in a neuromorphic architecture. 3 functional decisions regardingwhatshould be implemented, designers now can focus onhowa system should be implemented given a certain implementation strategy. This view ofeNDAopens up several opportunities. Firstly, it allows domain experts and hardware designers to work within a single unied framework, allowing improvements on one side to be directly transferred to another. For example, a new learning rule or network structure can directly be synthesized and made into a neuromorphic accelerator to solve problems in society. Secondly, the hardware designer now focuses exclusively on how hardware should be designed with direct access to a large number of domain-specic use-cases, allowing hardware decisions to be empirically explored systematically. Thirdly, domain experts can run their algorithms on more energy-ecient and faster FPGAs or even construct ASICs with the push of a button. The ow in aneNDAcan dier, but overall has the following functionality: • A Lexical analysis and language parsing step for understanding the neural algorithms to be incepted as a neuromorphic accelerator (these could rely on descriptions written in NEST, Brian2, or even NIR), • An intermediate representation (e.g., AST) encapsulating model dynamics and connectome and semantic analysis on said representation, • A series of high-level, hardware-agnostic optimizations, such as (for example) constant folding or common sub-expression elimination, • A model analysis step that understands and decorates the constructs with information critical for performance generation, such as whether a particular model is event-driven or continuous. • A network analysis step that analyzes and decorates the network with information such as information ow, bandwidth requirements, etc. • A hardware optimization step that performs hardware-specic optimization specic to the target, and • Neuromorphic synthesis, where abackendgenerates the neuromorphic platform based on the decorations provided by the other parts. Note that aneNDA-ow is nottiedto digital-only implementation, and dierentbackends can map the neuroscientic descriptions (often ODEs) to digital, analogue, or even mixed-signal components subject only to the availability of such a backend. 2.1 Syn2Logic: an eNDA prototype Syn2Logic is our prototype framework embodying the spirit ofeNDA, implementing theeNDA-ow of Figure1. Syn2Logic operates under a custom-designed, multi-paradigm language that combines (and is inspired by) elements of traditional hardware description languages such as VHDL (concurrent, strictly typed, hierarchical), with neural modelling languages such as NestML [28] and Brian2 [34], and a variant of Julia’s [29] multiple-dispatch functionality to eectively describe and build hierarchical neural networks. The language itself is object-oriented, L(1), where models and networks described can act as extendable prototypes, reducing code-bloat and increasing readability and code re-usability. In short, Syn2Logic combines the benets of a hardware description language with the familiarity of neural description syntax. The Syn2Logic model of computation has been created to be as compatible with existing frameworks as possible, simplifying the transfer of models, while still being hardware-friendly in order to facilitate mapping of descriptions to various types of hardware, such as digital and analog. The model of computation is divided into two types of components: amodeland anetwork. Amodelis the smallest unit that can perform computation, and is composed ofstate,update,events, andconduits (input) andoutputs. A model consumes (and computes) data from conduits and drives outputs. Model state consists of variables and constants. The model update describes how to go from timetto timet+1, most often (but not exclusively) using Ordinary Dierential Equations (ODEs). Model events are always-on, timeless monitors of the model state that trigger when a particular condition is reached. Generating output (=spikes) can only be done through events. The second part of the model of computation is anetwork, consisting of one or more models or subnetworks connected to each other. Here, the user describeshowa network is connected and how data is processed before entering each model. Each connection is event-driven, carries a token, and information is transferredinstantly. Furthermore, connections occurring at conduits can be processed, such as, for example, accumulating all incoming data, before sending it to a model/subnet, subject to how the receivers require the data. Information from outputs to conduits occurs instantaneously (unlike models whose state are synchronously updated), and combinatorial paths can form in a network (akin to their digital design counterparts). 4 2.1.1 Model Objects Model Denition A generic model is dened using the keywordmodelfollowed by optional prototype information, then state, and a body of ODEs and events. When a prototype statement is provided, the model inherits state and connectivity rules (see network, below) from the prototype, promoting code reuse and versatility. Listing 1: A base-class model of a neuron with empty body but with interface, followed by another neuron that uses the Neuron as a prototype. 1modelNeuron 2conduitIin:pA 3conduitspike_in:mV 4outputVout:mV 5varVm:mV= -65:mV 6constIconst:pA= 0,Vrst:mV= -65 7begin 8end 9 10modelLIF=Neuron(Vrst=-10) 11begin 12... 13end Model State State of the model containsvariables orconstants. A constant is a compile-time xed value that cannot be changed after the design of the neuromorphic architecture, while a variable is subject to change as a function of time (and available for observation from outside the circuit). Both constants and variables can be typed, where a type is either a base (or derived) unit from the International System of Units (SI), a scalar value, or a custom type. Metric prexes can be used to specify the magnitude of the unit (μ, M, G, etc.). The language is agnostic about the numerical size (in bits) of the variables or constants, leaving that decision to the compiler (or user) to decide. This allows variables to be size-agnostic, unlike (say) a language such as C or C++. All types of states can be made into an array or population. Modifying a variable can be performed in one of three ways:(i)externally by an end-user (when the system is not running),(i)through time-dependent ordinary dierential equations (ODEs), or(i)imperatively inside events. Listing 2: A constant (scalar) and a variable (nano Siemens) 1constAplus= 0.2 2varchem_GABA:nS= 3 Model Interfaces Interfaces are a special type of variable that are visible, have a sense direction (input or output), and are accessible outside of the model. They map very naturally to the neuromorphic concepts, since a neuron (or synapses, axons, astrocytes, glia, etc.) also shares the concepts of an input or output interface. There are two types of interfaces: a conduitandoutput. An output is an interface that can only be read from outside the model and is used by the model to transmit information out. An output in Syn2Logic is akin to an output port in (for example) VHDL, and may have only a single driver (avoiding race conditions). A conduit is an interface that can only be written into from outside the model and is used to transmit information into the model. Unlike an output, a conduit can have multiple writers to it, and it is up to the model to describe how to perceive those writes using collectives such assum,product, ormax. Listing 3: A conduit (pico Ampere) and an output (scalar) 1conduitI_in:pA 2outputVout Model ODEs ODEs describe how variables in the model change as a function of time, and map naturally to the dynamics of neurons and synapses. An ODE block, follows textbook conventions ( dX dt =.... ), allowing the code to be readable and relatable. ODEs at the language level have no time discretization; albeit (for digital hardware), hints regarding what kind of solver or timestep is needed for stable integration can be provided. Note that all equations in Syn2Logic are strongly typed: the type of the left-hand expression must match that of the right-hand expression. In our example, since Izhikevich operates on unit-less variables, this means that we make use of casting expressions to force certain equations to be – in 5 our case – of type mV, and that we properly divide it by time. Note that the magnitude (e.g. the resolution of1: mV+ 1: GV) may dier, and our compiler will insert required adapters between expressions at a later stage in the pipeline. Listing 4: A dierential equation for LIF neuron membrane dynamics 1dVm/dt= (Iconst+Gexc*(Eex-Vm) +Ginh*(Ein-Vm) -gL*(Vm-EL))/Cm Model Events Events are anonymous functions thatcanmodify model state asynchronously and atomically (appearing, to the system, instantaneously), but can only be triggered upon a condition. A condition could be, for example, when a model of a neuron receives an action potential or spike from other neurons. Events that are triggered only as a function of external conduits are asynchronous (and can occur without advancing time), while events that are a function of at least one state variable are called synchronous (and can occur only during state update). Asynchronous events are important as they enable (for example) lazy updating of model state and pass-through (combinatorial) relay of signals (an event based on a conduit that writes to an output relays information downstream instantanously). Listing 5: An event that activates if internal state Vm>-30 and writes to output port Vout while resetting Vm to -60:mV, and an event that triggers when a conduit receives spikes, and accumulates the value of all spikes (::sum) on the conduits into variable Hinh 1event(Vm> -30:mV) 2Vout=Vm,Vm= -60:mV 3end 4 5event(I_in) 6Hinh=Hinh+I_in::sum 7end 2.1.2 Network Objects Network Object Anetwork object in Syn2Logic acts as the blueprint for how to wire together populations of models (or other nets) to create a larger, more capable, component. Often, the blueprint of a neural network dictates its functionality, and we see many such examples from literature, including central pattern generators (CPGs) [53], winner-take-all (WTA) [54], and even full-brain connectomes of invertebrates such as the nematodeC. elegans[55] and the fruit yDrosophila melanogaster[56]. Information between network objects is send instantaneously from sender (conduit) to receiver (output). Describing a network object involves three things:(i)instantiate population instances of models or networks and their conguration (e.g., changing constants). Each instance gets its own copy of the model state, and it is possible to override any value at instantiation (e.g., giving one neuron stronger drive than others),(i)describe how populations wire together using well-known connectivity schemes such asall2allorone2one, connecting outputs of some models to conduits of others, and(i)a network can (as a model) have their own conduits and outputs connecting internal populations to propagate information in and out of the network. Listing 6: A simple WTA network that instantiates NZ neurons that inhibit each other and compete for activation. 1netWTA 2constNZ= 3 3conduitcinp[NZ]:mV 4outputcout[NZ]:mV 5objpop[NZ]:LIF() 6begin 7one2one(cinp[*]⇒pop[*].spike_in) 8one2one(pop[*].Vout⇒cout[*]) 9one2all(pop[*].Vout⇒pop[*].spike_in) 10end Rule-based Connectivity Connecting outputs of one model to the input of another is trivial as long as the types match, such as connecting an output of typemVto an input also of typemV. However, this quickly becomes very verbose and unclean code-wise as it combineshowsomething is connected with thetopology. In Syn2Logic, we decouple how something is connected 6 from the network itself by usingrule-basedconnectivity. Aruledescribes how amodelornetconnect to other components in the system. For example, a simple synapse would connect its output (conductance) to a neurons conduit, and a more complex plastic synapse would also connect the post-synaptic neuron’s output back to itself. Furthermore, rules are inherited through prototypes, meaning that if a rule connecting our basic emptyneuron(dened above) with a basic emptysynapseexists, then all variants of neurons and synapses inherited from their respective prototype will know how to connect unless a new rule for that model/net is written. The concept is similar to Julia’s multiple dispatch. Listing 7: A rule describing how a WTA network connects to another WTA network, in this case by having each entry in the connecting WTA inhibit corresponding entry in the destination WTA. Such a network is useful for when, for example, creating neuromorphic constraint satisfaction solvers. 1rulesrc:WTA⇒dst:WTA 2begin 3one2one(src.cout[*]⇒dst.cinp[*]) 4end Template-based Instantiation Finally, by decouplingwhatconnects to what fromhowit connects, we can allow templates. A template is a construct that allows a network to operate on generic models/networks, which are resolved dynamically at compile time and whose connections use the ruleset that has been dened. Templating allows writing generic code for constructing a network without specifying what type of neuron or synapse model is being used. For example, one can dene a network describing a microcircuit using a template and then easily change the underlying neuron of the model from LIF to Hodgkin-Huxley, or even to other sub-networks with the change of a single line (or during instantiation). Listing 8: A simple two-neuron oscillator built using templates (TNeurondefaults to LIF,TSynapsedefaults to AMPA) allowing any template to be changed to any other model (or network) assuming the rules for connecting them exist. 1netHCO 2templateTNeuron=LIF() 3templateTSynapse=AMPA() 4objneu[2]:TNeuron() 5objsyn[2]:TSynapse() 6outputspkout[2]:mV 7begin 8one2one(neu[0]⇒syn[0]) 9one2one(syn[0]⇒neu[1]) 10one2one(neu[1]⇒syn[1]) 11one2one(syn[1]⇒neu[0]) 12one2one(neu[*]⇒spkout[*]) 13end 2.2 Example Network To demonstrate a complete example, consider Figure2:a, where we see a network not entirely unlike the nervous system for theC. elegansnematode, ported to the Syn2Logic language from c302 [55]. Red, blue, and green nodes correspond to dierent neuron types (inter-, motor-, and somatic-neuron), and gray- and white-boxes correspond to plastic and non- plastic synapses, respectively. Our example network works with STDP synapses, which the c302 does not, and this is only to show the dierent perspective of the Syn2Logic language (we construct a more faithful c302-variant later in3.3). Figure2:b shows an enlarged part of the graph, showing a motor neuron (red) and its description in the Syn2Logic language (Figure2:c). A plastic STDP synapse (Figure2:d) is connected to the motor neuron using the specied ruleset (Figure2:e) by connecting the output conductanceG_outto thechem_inconduit of the neuron, and connecting the spiking outputV outof the neuron back to theV postconduit terminal of the synapses, completing the connection. A simpler non-plastic synapse is shown in Figure2:f. Parts of the top-levelC. elegans-like Syn2Logic description are shown in Figure2:a, where the neuron and synapses objects are created followed by a long connectivity list. This is a detailed and verbose way of describing each connection in the system. An alternative – and more general – is shown in Figure2:g, where we create a generic accelerator with 302 neurons and302 2 STDP and inhibitory synapses, respectively, and connect all of them together. Smaller and more elegant, this description requires the users to actively program the state of the accelerator prior to execution (similar to how neuromorphic systems such as Intel Loihi are programmed). 7 (b) (c) (d) (f) (e) (a) (g) Fig. 2: A Syn2Logic graph (rendered using dot and based on theC. elegansnervous system), showing the top-level Syn2Logic code describing it (a), a zoom-in of a motif (b) where we see the neuron model (c), the STDP synapse (d), and the rule (e) on how to connect a STDP synapse to the neuron, which is also visible in the motif. We also see the simpler non-plastic synapse (f). Finally, we see a generic description of the accelerator (g) that is condensed but requires the user to congure it (unlikea, whose connectivity is sparser but immutable). 8 2.3 Syn2Logic Neuromorphic Backend As with a regular compiler, Syn2Logic can have multiple backends transforming the intermediate representation into a digital, analog, or mixed-signal neuromorphic device, each with their own characteristics, strengths, and weaknesses. For example, a neuromorphic device targeting a specic Internet-of-Things (IoT) use-case will likely use a backend focusing on creating an ASIC with low power consumption, while a generic design targeting a high-performance, high-capacity network would prefer a top-tier FPGA backend. Fig. 3: A generic view of a model component generated by our Syn2Logic class4-backend. We see an Izhikevich model with several state variables, and each variable is daisy-chained on the scan-chain, which goes serially through all components in the system and can be congured from outside. The model state is connected to a generated data path that solves the ODEs and handles events. Conduits are currents from (typically connected synapses) that are added together to provide reduction functionality at the neuron side. Each conduit and output has a token (a spike-enable) signal, indicating a valid value (not entirely unlike data-ow). To illustrate the concept, we developed a backend that generates digital hardware that embraces the spirits of neuromorphic computing [57], where the substrate becomes the computation (the entire network is placedin silico, with no time multiplexing of data paths). The output of our backend is a component shown in Figure3(in this case, an Izhikevich neuron). The generated neuromorphic system meets the neuromorphic requirements described by Kudithipudi et al. [17], and is considered a class-4 system per Szczerek and Podobas’ taxonomy [16]. Our backend takes the intermediate representation and generates a digital neuromorphic system(i)whose components are discretely and spatially placed on the underlying silicon,(i)communicates in a sparse and event-based fashion, (i)implements data-paths for updating neural state using xed-point representations, and(iv)is deterministic in that advancing one time step takes exactly one clock cycle. The strengths of our backend are that it generates high- performance yet deterministic neuromorphic systems without reliance on external peripherals (e.g., DDR4), and where it is therefore the closest to nervous systems in nature. The weakness is that it is not very scalable, and suitable only for small-to-medium sized designs. Additionally, our backend accepts a number of optimizationknobswith which the user can adjust or control the quality of the neuromorphic hardware generated: • Fixed-Point Width (M:N): A user can specify the size of state in terms of mantissa- and fraction-bits, which can trade accuracy for smaller silicon, • Timestep (TS): A user can select how fast time advances in the neuromorphic device. A large timestep is faster but can lead to instabilities, • Per-Model Bandwidth (PMW): A user can specify the bandwidth of conduits into a model, and can optimize for the fact that spikes are very sparse at the risk of dropping information in times of high activity. 9 • Fused operations (FO): Forces fused data-paths and reduction adapters operating without loss in accuracy, and rounds only at the end of the computation, • Approximate Constants (AC): allows approximating constants to save silicon area, relying on the observation that some constants consume a lot of area to be exactly (if at all possible) dened. 2.3.1 Syn2Logic Complete Internal Flow The internal Syn2Logic compilation ow follows our proposedeNDA-ow closely. To compile a Syn2Logic (.s2l) source le into a neuromorphic system in RTL, we perform the following steps: • Lexical analysis: Our Flex-generated scanner deposits tokens onto a double-ended queue consumed by the recursive-descent parser. The lexer normalizes the language’s notation: the equivalent derivative spellingsX’and dX/dtare mapped to a single ODE token, SI units carry their metric prex as a power-of-ten magnitude, and the identier rule consults the symbol tableduring scanning, such that an identier with a registered datatype sux (e.g.,mV) is emitted as a typed token. • Syntactic analysis:and parsing is performed by a hand-written recursive-descent parser dispatching on the constructstype,model,net,rule, andbuild. Expressions are parsed with a two-stack operator-precedence scheme; integer exponents expand into repeated multiplications at parse time. Postx analysis yields function calls, array accesses (including ranges and the*wildcard), member accesses,::sum/::num/::max/::product reductions, and::typecasts. For models, the parser collects storage declarations (const,var,conduit, output) together with ODEs, algebraic equations, andeventblocks; the left-hand side of an ODE is intentionally represented asX1 msso that dimensional analysis ofdXdtremains well dened. Nets comprise object and template declarations and connection commands, whereas rules are registered under the mangled name srcType+dstType. Prototype derivation (model Foo = Neuron(...)) clones the prototype’s AST and overrides its constants from the supplied dictionary. Finally,parse_build()deep-clones the build target, applies its dictionary, and invokesInstantiate,AnalyzePorts, the optional visualisation passes, andClass4. –Verication: This pass constitutes the principal semantic analysis and is re-executed for every instantiated clone. It resolves all symbols (and decorates the tree) and performs dimensional type checking over the SI unit system: addition, subtraction, comparison, assignment, and ODEs require identical dimensions on both sides, whereas multiplication and division combine dimensions algebraically; magnitude discrepancies merely warn, deferring toBalanceTypes. The pass further propagates thewriteable,is_const, and event-drivenattributes (a model writing its outputs solely in such handlers is itself classied as event- driven) and enforces the language’s structural invariants: single-writer outputs, no variable/output/self reads in equations, reductions restricted to conduits (recording thereduce_*attributes consumed downstream), array dimensionality, function signatures, and constant, type-correct initialisers. –Print (optional)A diagnostic pass that emits the fully attributed AST; its output is suppressed at default verbosity and exposed through command-line options. –Instantiate: This pass elaborates the declarative design into a concrete instance hierarchy: for a Net, it rst applies the sub-sequenceVerify→StripTypes→ConstFold→DivToMul(reducing array bounds to literals) and then, for each declared object, clones the referenced model or net, assigns a globally unique name to preclude duplicate VHDL entities, applies the parameter dictionary, attaches the clone viasetImplementation(), and recurses depth-rst. For aModel, the sub-sequence Verify→BalanceTypes→StripTypes→ConstFold→DivToMul→Verifyis applied, after which the model consists of dimensionless, constant-folded arithmetic suitable for hardware mapping. ∗BalanceTypes: Source programs may freely mix magnitudes of a common dimension (e.g., millivolts and volts); for every binary statement, this pass compares the magnitude exponents of the operands and, where they dier, rewrites the right-hand side with an explicit multiplication or division by10 k , so that the subsequent erasure of units incurs no numerical loss. ∗StripTypes: This pass erases the unit system: cast nodes are replaced by their operand, the implicit 1 mson ODE left-hand sides is removed (right-hand-side divisions are preserved), and all declared symbol types are reset to the dimensionless type, leaving a purely numerical program. ∗ ConstFold: Constant symbols are substituted by their values, operators over two literals are collapsed, and the identitiesx0,x−0,0−x=−x,x·0=0, andx1=xare applied. As instantiation converts model parameters into constants, this pass eectively specialises each instance’s equations and renders divisors literal forDivToMul. ∗DivToMul: Since a hardware divider is substantially larger and slower than a multiplier, every division by a literal cis strength-reduced toX·1c, the reciprocal being evaluated at compile time;X1is eliminated. 10 ∗Build command interpreter:Buildis the common base class ofAnalyzePortsandClass4; subclasses override a virtualconnect()method invoked once per resolved point-to-point link. Its Commandvisitor expands wildcards and ranges into index sets (verifyingone2onecardinality) and enumerates index pairs for primitive endpoints. For object-to-object connections it performs rule expansion: the rule registered undersrcType+dstTypeis cloned, itssrc/dstplaceholders are substituted with concrete array accesses (ReplaceId), the result is re-veried, and the rule’s commands are re-executed per index pair, unfolding a single net-level command into all of its port-level links. ∗AnalyzePorts: The hardware required at a port depends on the opposite endpoint of each connection: a conduit read asIin::sumobliges every connected source to export a value bus in addition to its spike bit. Inheriting theBuildinterpreter, this pass re-executes all connection commands, transfers each destination conduit’sreduce_*attributes onto the corresponding source ports, and recurses through the instance hierarchy, thereby determining which reduction adaptors and_valside channels the backend must generate. –DotGraph/DotGraphPop: Optional passes rendering Graphviz visualisations of the design at object and population level. The previous Figure2was generated using this pass. • Backend (Class4): The nal backend produces the nal RTL for the neuromorphic system, and is composed of four parts: expression mapping, dierential equations/state mapping, model emission, and network emission: –Expression Mapping: Code generation proceeds bottom-up: each AST node deposits a"mapped"signal annotated with exactm, nbit bounds. Literals are quantised to their minimal exact format, further reduced under–round-constants. Bit growth is tracked exactly (addition:max 1; multiplication:m l m r 1; etc.), whereuponmaybeFuse()resizes each result toM:N; under–fused-opsthe wide intermediate is instead retained, exchanging area for a datapath free of intermediate rounding. Comparisons yield single-bit when/elsesignals, and reduction nodes read the conduit’s precomputed port. The functionsexpandlog are expanded inline into Taylor-series datapaths, the former via base-2 decomposition with a barrel shifter. –ODEs, events, and state threading.ODEs are integrated by the forward Euler method:X f·T Sis computed combinationally but not committed to the register, being published instead in a per-variableNextStatemap. Within an event, reads are redirected throughNextState, so that a threshold condition observes the freshly integrated value (“integrate-then-test”, as in Brian2/NEST) and an accumulating assignment composes with, rather than supersedes, the ODE step; each event assignment becomes a multiplexer over the value produced thus far, replacing the correspondingNextStateentry; output assignments are emitted combinationally (event-driven models) or as guarded sequential statements. Only upon completion of the model visit is each variable’s nal value committed to its state (a part ofconfigon the scan-chain) — one register write per variable per timestep, avoiding VHDL’s last-assignment-wins semantics. Reads outside events continue to observe the registered value, preserving the simultaneous (Jacobi-style) integration of coupled ODEs. –Model synthesis: The backend produces a fully parallel implementation with co-located memory and computation (class-4 [16]): one VHDL entity per model and one structural entity per net, appended to out.vhdltogether with a JSON device tree (out.json, which describes what variable is located where on the scan-chain). Its parameters (M:Nformat, timestepTS,pmw,round_constants,fused_operations) come from the symbol table. Eachvaris realized as ansfixed(M downto -N)signal aliased onto a slice of a singleconfigshift register, with its reset value, read alias, and bit address recorded in the device tree; the register simultaneously serves as a scan chain (config_in/out/en) for state load and read-back. Conduits map to spike input ports (with_sum/_num/etc. side ports where required), and outputs to output ports (with a_valbus where a downstream reduction consumes the value). –Network synthesis: For aNet, the backend rst recurses into each object’s implementation and then constructs a structural architecture. Re-executedconnect()calls accumulate per-port lists of mangled signal names (obj_idi_port_idj); the instantiation loop then emits oneport mapper array element, in which spike inputs are combined by disjunction over all sources,::numis realised as an adder over spike bits,::sum as a balanced adder tree over_valbuses (resized after each addition, of depth⌈log 2 K⌉), and::productas a multiplication chain. For0<pmw<1, a reduction’sKinputs are partitioned into⌈K·pmw⌉bins of one priority-selected value each, trading connectivity for area. Per-model scan chains are concatenated through a config_chainsignal; the architecture is appended toout.vhdland the device tree written toout.json. • Post-Emission ows: Following the backend,parse_build()invokes the ow generator selected by–flow —GenCadence(Genus+Innovus/ASAP7; default),GenOpenROAD(NanGate45, unused in this paper, but we do have preliminary support for OpenROAD [58]), orGenQuartusAgilex7— each bundled without.vhdlinto <flow>_flow.tgz;–testbenchadditionally generates a spike-countingGenMeasureOutActivitytestbench. 11 Fig. 4: Current-Frequency response (i-F) for four neuron models with reference framework Brian2 and Syn2Logic, including (a) Leaky Integrate-and-Fire, (b) Izhikevich, (c) AdEx, and (d) Hodgkin-Huxley. 3 Results 3.1 Neuron Correctness and Exploration We start by exploring the correctness results for our proposedeNDA-ow for four dierent neuron models: Leaky Integrate and Fire (LIF), Izhikevich, Adaptive Exponential Integrate and Fire (AdEx), and the Hodgkin-Huxley model, in rising order of complexity. For each evaluation, we see the ring rate of the neuron as a function of the internal constant current, a well-known correctness experiment. We compare to Brian2 as a golden reference, and use Normalized Root Mean Square Error (NRMSE) as a measurement for how well the dierent implementation match our Brian2 reference. The LIF model – a cornerstone neuron model in neuroscience and neuromorphic engineering – is shown in Figure4:a, where we see the f-I response curve for both the Brian2 reference implementation and the Syn2LogicQ 32:24 high- delity variant. Overall, this high-delity Syn2Logic variant faithfully follows Brian2’s LIF dynamics, and – for the sampled input current points – yields the same 380 pA rheobase current, which is when (for our samples) the neuron starts ring. The error between this high-delity Syn2Logic LIF model and the Brian2 reference is as little as 0.4% NRMSE. The LIF model does not need an expensiveQ 32:24 format to work well. In fact, by applying fused operations, we can operate with state variables at aQ 7:7 format with less than 5% NRMSE, and we are forced to widen the data-path to aQ 16:6 format if we disable fused operations and force-round results after each operation in the datapath. The NRMSE <5% requirement follows the trend of the Brian2 curve, albeit with some small over- and undershoots in the frequency for a given input current. The Izhikevich model, which is more complex than the earlier LIF model, is shown in Figure4:b. As with the LIF model, the Izhikevich Syn2Logic variant follows the Brian2 model faithfully, yielding identical rheobase currents for the tested current points and follows the curve near-exactly, with – interestingly – the non-fused version reaches 0.0% NRMSE error compared to Brian2, and the fused variant reaches 0.7% NRMSE. As with the LIF model, the Izhikevich model does not need the fullQ 32:24 format, but – assuming an NRMSE <5% ratio can be tolerated – can work well with aQ 6:9 fused variant or aQ 13:8 non-fused variant, showing small under- and overshoots in the graph relative to the Brian2 reference value. 12 The AdEx model is even more complex than Izhikevich, containing more complex ODEs and also the hardware- unfriendlyexpfunction. We see the comparison between Syn2Logic and Brian2 in Figure4:c. The high-delity Q 32:24 Syn2Logic variant behaves identically with the Brian2 reference model, with a rheobase current of 580 pA. The fused-op variant stays at 0.0% NRMSE compared to Brian2 until we drop to 8 fractional bits, while the non-fused variant is a bit more chaotic. For fused-operations, aQ 9:6 value is enough to stay within NRMSE <5% (with notable undershoots compared to the Brian2 reference) while the non-fused variant reaches a 2% error rate atQ 16:7 . We end our validation experiments by comparing the Hodgkin-Huxley model on Brian2 and Syn2Logic, shown in Figure4:d. The H-H model is a complex neuron model, with multiple ODEs and a large number of multiplications, divisions, andexpoperations. While the Syn2LogicQ 32:24 variant reproduces and follows the Brian2 model rather well, it still has an NRMSE of 0.9% that cannot be reduced; interestingly, in xed-point representation, larger data type is not better, asQ 18:14 yields better NRMSE thanQ 32:24 . This could be attributed to Brian2 model’s IEEE 754 numerical representation being better than the xed-point representation our backend operates on. The fused variant can be as small asQ 7:17 while keeping within a <5% NRMSE while the non-fused variant requires more integer bits and is atQ 16:14 . 3.1.1 Discussion: Neuron Models in Neuromorphic Systems? Table 1: ASIC cost of the four neuron models at their faithful (≤5%) xed-point format, fused vs non-fused ops (ASAP7 7 nm, Cadence Genus estimation).Area savingand ΔF max are the non-fused variant relative to fused. Model OpsAreaF max AreaΔF max (μm 2 ) (MHz) saving (MHz) LIF fusedQ 7:7 475.6137 7.6%−8 non-f. Q16:6439.4129 Izh. fused Q6:9826.2127 19.3%−6 non-f.Q 13:8 667.0121 AdEx fusedQ 9:6 1020.099 23.2%−34 non-f.Q 16:7 783.765 H fusedQ 7:17 52 27230 74.7%0 non-f.Q 16:14 13 21230 Synthesizing the neurons using Syn2Logic and Cadence Genus, we observe several trends, shown in Table1. The rst observation, which is rather intuitive, is that the more complex the neuron model, the more area it consumes and the slower it operates. For example, the LIF model can operate at 137 MHz, consuming less than 500μm 2 in area, while the H, which is many times more complex, is signicantly slower and can be more than 100x larger. The second observation is that fused data paths can give the neuromorphic system higher performance. Rounding xed-point numbers can be expensive, and by rounding only when you store the result back, you can increase the operating frequency of the circuit. This increase is visible in LIF, Izhikevich, and AdEx, but is most notable in the latter (nearly 50% increase in clock frequency). However, this increase in clock frequency is not free, as the fused data paths are wider and thus – as a consequence – cost more area, whereas the non-fused version can have a footprint between 7.6% and 74.7% smaller than its fused counterpart. An interesting observation is that, despite using a rather small, 7 nm, predictive PDK, our described neurons are still far away from their biological counterparts. Granule cells (among the smallest cells in the cerebellum, 8μm 2 ) [59], cortical pyramidal cells ( 25μm 2 ) [60], and the large Betz cells ( 100μm 2 ) [61] are still 55x, 18x, and 4.4x smaller than even our most pruned and smallest LIF model, leaving ample future opportunities for improvements. Finally, a word of warning: the exact width of the xed-point representation is – as we will see in our use-cases – very use-case dependent. A computational neuroscientist might accept a NRMSE<5% (or stricter), or might opt for a larger data-path that is much larger giving more details. A neuromorphic application, on the other hand, might actually work with a signicantly smaller data-path– an observation we will see later when creating our neuromorphic Sudoku solver. 13 3.2 Synapse Correctness and Exploration Fig. 5: Large-scale evaluation of four plastic synapse models (PairSTDP, TripletSTDP, RSTDP, and BCPNN) in the Syn2Logic framework, with the tested induction protocol (pre- and post-synaptical activity) and the change in weight (w) and other state variables. For each model we also show its sensitivity to xed-point precision quantization. Next, we quantitatively verify the correctness and explore the data-path pipeline for four well-known plastic synapse models and a specic induction protocol: Pairwise STDP, Triplet STDP, RSTDP, and BCPNN. The results are shown in Figure5. 14 Figure5:a shows the classical pairwise STDP rule based on traces. Here, we created an induction protocol that spans 3.6 seconds of simulated time and rst encourages synapse potentiation (the weight w increases) for the rst half seconds by driving post-synaptic spikes directly after pre-synaptic spikes, and then induces synapse depression (the weight w decreases) during the remaining half seconds of the simulation. The functionality, the traces, and the depression/potentiation are in line with the expected functionality of STDP. Furthermore, what is interesting is that STDP, as long as the weights are clipped to a maximum, can tolerate a data-path width reduction as low asQ 2:8 , yielding an NRMSE of 3.5% and 4.1% for fused- and non-fused data paths alike; going further signicantly decreases the performance of the learning rule compared to its golden reference. Figure5:b shows the TripletSTDP rule with a similar induction protocol as the Pairwise rule, but containing twice as many trace variables. The rule functions as expected in both depression and potentiation mode, and — due to the more complex nature of the rule — requires more fractional bits compared to its pairwise counterpart, landing atQ 2:9 to maintain 2.8% and 3.5% for the fused- and non-fused variants’ NRMSE, respectively, over the golden reference. Figure5:c shows the reward-modulated STDP rule (RSTDP), with a more complex induction protocol consisting of both causal and delayed rewards, as well as no rewards and anti-rewards. We see how the dierent pre- and post-traces induce changes to the synapse strength based on the eligibility trace to the synapse weight. As with the TripletSTDP rule, we see the RSTDP rule for the proposed induction protocol can require as little as aQ 2:9 precision, reaching 1.30% and 0.20% variants’ NRMSE, respectively for the fused- and non-fused variants, over the golden reference. Finally, we take on a much more complex learning rule in Figure5:d, where we see the Bayesian Condence Propagation Neural Network (BCPNN) learning rule. Here, we use a complex induction protocol that includes ve dierent activities on the eligibility traces (correlated, independent, anti-correlated, silent, and post-muted). In addition, we compare our Syn2Logic-generated functionality against the reference Brian2 model. At aQ 24:24 data-path, our Syn2Logic variant mimics the Brian2 model rather exactly in all regimes. In fact, we can reduce the data-path width to as little as an Q 8:18 (non-fused) andQ 8:19 (fused) width while still being 0.92% and 3.5% NRMSE compared to theQ 24:24 variant. In the end, whether a plasticity rule works or not is likely scenario-dependent, and could allow for further reductions than shown here. For example, if an NRMSE<15% error rate can be tolerated (the gray-shadow behind the graph in Figure5:d), thenQ 8:14 format should suce. Syn2Logic can and will be used in the future to quantify the impact of plasticity rules and their impact from within more complex use-cases. 3.2.1 Discussion: Which Synapse Model to use in Neuromorphic Systems? Table 2: ASIC area of the four plasticity rules at their faithful (≤5%) xed-point format, fused vs non-fused ops (ASAP7 7 nm, Genus synthesis estimations).Area savingis the non-fused variant relative to fused. RuleOpsAreaArea (μm 2 ) saving Pair fusedQ 2:8 91.9 34.2% non-f.Q 2:8 60.4 Triplet fusedQ 2:9 374.4 71.7% non-f.Q 2:9 105.9 RSTDP fusedQ 2:9 202.3 35.4% non-f.Q 2:9 130.7 BCPNN fusedQ 8:19 1 269.9 −9.2% non-f.Q 8:18 1 386.9 The synthesis results for the synapses are shown in Table2. As expected, the Pairwise-STDP synapse is by far the smallest, consuming as little as 60.4μm 2 area, with the Triplet-STDP (larger fused-variant) and RSTDP (larger non-fused variant) being similar in area, and BCPNN – being the most complex and uses alogfunction – is the most expensive at 1269.9μm 2 . As expected, the fused variants are larger than their non-fused counterparts, with the highest benet observed in TripletSTDP (71.7%). Interestingly, the BCPNN Q 8:19 version synthesized was smaller than the non-fused version. While the dierence in hardware cost is – as expected – dierent in the various plastic synapses, it does raise another question: how much "learning" capacity does a synapse actually bring for the silicon footprint it consumes? If a neuromorphic IP component has a silicon budget of 0.1m 2 for a device that should learn online using plastic synapses, should that silicon be spent on 78 BCPNN synapses, 765 RSTDP synapses, 944 TripletSTDP synapses, or 1655 STDP synapses to perform the best? Likely, the answer depends on the use-case, where some use cases might benet from the more advanced learning of BCPNN synapses while others favor the simpler (but more) Pair-STDP synapses. Independent of which, the amount of "learning" per silicon area is seldom discussed, but should be quantied in the future, since – in the end – it is the hardware implementation that in parts dictates the success (through lowered execution time or reduced power consumption) of putting neuromorphic systems to good use. An example metric could be (for example) Silicon Learning Fidelity, SLF= #Synapses m 2 for a particular technology node and iso-delity. We end the discussion by comparing our results to biology 5 . Unlike neurons, whichcould(the smallest LIF model) be between 4x-55x larger than biological neurons, the same – unfortunately – does not hold for synapses. A typical synapse 5 Where, to be fair, synapses are 3D and not 2D as the silicon we produce, so the comparison is not entirely faithful. 15 in the human brain is on the order of 0.1μm 2 [62] in area, which is a factor 600x smaller than our PairSTDP, 1059x smaller than TripletSTDP, 1307x smaller than RSTDP, and 12699x smaller than a BCPNN synapse. Granted, our silicon synapses run multiple times faster (opening up the possibility to time-multiplex synapse data paths, which is what many neuromorphic designs do) at the expense of reconguration. In short, creating capable, capacitive, and plastic synapses that bridge the gap between biological systems and silicon is more of a challenge than placing a lot of neurons on a chip. 3.3 Fastest Level-A (LIF-based)C. elegansSimulation Fig. 6: (a-c) Reference jNeuroML, Brian2, and NEST, spike plots for theC. eleganssimulation, (d) theQ 32:32 full-precision Syn2Logic spike plot, (e) the impact on data-path width and per-model bandwidth on the error rate, and (f) the nal hardware-friendly neuromorphic system. Next, we turn our attention to the full-scaleC. elegansconnectome shown in Figure6. Figure6:a-c shows spike raster plots for the network running 0.8 seconds of simulated time 6 on the well-established simulators jNeuroML, Brian2, and NEST, respectively. The dierent simulators produce near-identical ring rates (25 Hz for NeuroML and Brian2, 24.9 Hz for NEST) but with a dierent ring rate distribution and (more or less) equal number of total spikes (6040, 6041, and 6009 for jNeuroML, Brian2, and NEST, respectively). OurQ 32:32 Syn2Logic description – in Figure6:d – of theC. elegansmatches the results of jNeuroML and Brian2, showing 25 Hz mean frequency, 6042 spikes, and near-identical ring rate distribution. Unfortunately, such a largeQ 32:32 variant would not t on the FPGAs we use, and so there is a need to design-explore to reduce the size of the nal accelerators. We explored parameters that govern the xed-precision size and the per-model bandwidth, with the rst being motivated by our earlier neuron sensitivity study (Section3.1) while the second being motivated by the fact that biological SNNs – such as the presentC. elegans– are very sparsely active, where each neuron (on average) is active only 0.25% of the timesteps– a clear sign that each neuron does not need full bandwidth from each of their synapses. Figure6:e shows the tradeos, showing the error (in % of spikes) as a function of per-model bandwidth for a number of xed-point variants. We see that already at 90% bandwidth reduction (PMW=0.1), most variants reach <5% of error compared to theQ 32:32 reference, where 80% and less reach <2.5% error.Q 7:12 andQ 7:13 variants have too few fractional bits to perform well, irrespective of per-model bandwidth, and instead top out at 25% and 12% error, respectively. AQ 7:15 variant strikes a strong <1.5% error rate, keeping only 20% of its incoming connections, whose spike raster plot we see in Figure6:f with 5952 spikes and a 24.6 Hz mean neuron ring rate. As for rounding constants, anything larger than 1% rounding signicantly impacts the results negatively. 6 The full simulation is 1 second, but the rst 200 ms the network is mostly silent before activity starts. 16 Fig. 7: Performance comparison between simulation and Syn2Logic FPGA and ASIC auto-generatedC. elegansaccelerators. Table 3: FPGA and ASIC Synthesis infor- mation forC. elegans Agilex7 Logic utilisation (ALMs) 219,330 / 487,200 (45 %) Dedicated logic registers 55,420 DSP blocks3,926 / 4,510 (87 %) Clock frequency56.02 MHz ASAP7 Std-cell area277,499μm 2 (0.277 m 2 ) Cell count2,808,514 f max 126.9 MHz Total power56.4 mW Table3shows synthesis results for theQ 7:15 version with 20% per-model bandwidth and 1% rounding, which ts on our Agilex7 FPGA device, occupying half the logical resources and most (87%) of the DSP resources, making it DSP-bound. It reaches a peak clock frequency of 56.02 MHz. The same design, synthesized using Cadence Genus for the ASAP 7nm PDK, yields a 0.277m 2 design (2808514 standard cells) with a peak clock frequency of 126.9 MHz. In Figure7, we put our accelerator performance numbers into perspective against current state-of-the-art simulators; we see that our FPGA accelerator can simulate theC. elegansconnectome 392x, 3,641x, and 143,971x faster than NEST, Brian2, and jNeuroML, respectively, running on a large multithreaded server. Furthermore, should our ASICC. elegansaccelerator ever be taped out, we would observe a 2.26x speed-up over the FPGA results. To the best of our knowledge, we have shown how to use Syn2Logic to obtain the fastest level-A (LIF-based)C. eleganssimulation existing today. Our FPGA accelerator runs close to 6000x faster than real-time– performance levels that could eventually open up research into understanding plasticity in the worm, neuromorphic and neuroAI crossover, or (eventually) closed-loop experiments. 3.3.1 Discussion: eNDA for use in Neuroscientic Simulation The speed of neuroscientic simulation is considered one (of four) grand challenges [38] in the pursuit of a deeper understanding of how the brain functions. In particular, faster-than-real-time simulations allow researchers to study the long, slow processes that govern many complex dynamics in the brain. Despite its simplicity, theC. elegansmodel is still not yet fully understood, and by using oureNDA-ow to produce high-performanceC. elegansaccelerators that execute between 392x-143971x faster than simulators, we can facilitate faster-than-real-time exploration ofC. elegans, allowing plasticity experiments, neuromorphic/neuroAI crossover, or even (in the future) closed-loop experiments. In the future, we want to extend oureNDA-backend to support larger connectomes, and to accelerate the recently charted connectome of theDrosophila melanogaster[56] (the common fruit y). 3.4 A Fast Neuromorphic Sudoku Solver Now we turn our attention towards using SNNs to solve practical optimization problems. One such problem is Sudoku, which represents a canonical constraint satisfaction problem (CSP), with a structure of 81 variables, each containing a digit between 1 and 9, and constraints that enforce all-dierent on rows, columns, and 3x3 quadrants. The Sudoku problem is NP-complete and has a form that can be adapted to other problems (scheduling, resource allocation, etc.). Furthermore, it is a standard benchmark to solve. Finally, while prior work has shown SNNs to be capable of solving Sudoku, so farnone has ever been able to compete with existing ILP/CP solvers or custom solutions. 17 Fig. 8: (a) The hardware architecture for solving Sudoku puzzles using our Syn2Logic accelerator, and (b) the performance comparison between CP-SAT, SCIP, tdoku, and our Syn2Logic accelerator per-puzzle solution time. Table 4: FPGA and ASIC synthesis (ASAP7 7 nm, Genus synthesis estimations) results for our Sudoku accelerator. Agilex 7 Logic utilization (ALMs)426,278 (87%) Dedicated logic registers75,315 DSP blocks1,823 / 4,510 (40%) Block RAM / memory0 (none used) Clock frequency (F max )63 MHz ASAP7 Standard cells2,033,761 Cell area177,086μm 2 (0.177 m 2 ) Total power61.3 mW Clock frequency (F max )208.2 MHz To solve Sudoku, we designed a network based on the Izhikevich model with added local long- and short-term annealing (escape currents) to avoid being stuck in local (incorrect) minima—a well-known problem in SNN-based solvers. In addition, we performed heavy parameter search to nd fast-performing parameters. In the end, the parameters we found working well were:a=0.0267,b=0.25,d=7.06, Δt=2.382,I const =14.82,I set =20.77,w syn =13.5, τ s =12.58,Δθ=0.398,τ θ =90.5,R amp =17.63,τ r =65, v th =32,c=−65, which were then quantized and optimized for anQ 8:2 format. There are a few very interesting things with the above param- eters. Firstly, we treat the integration time step as a free parameter to optimize, which resulted in a very large time step of 2.382 ms — more than 20x larger than traditional neuroscientic simulations of the Izhikevich model (0.1ms). Secondly — and this is counterintuitive — we found that the model worked best with a very small number of fractional bits, and actually aQ 8:2 format was shown to perform better than higher-precision alternatives. These two observations run counter to standard practices for using SNNs to solve optimization problems. Furthermore, these optimizations — in particular the second one — are very hardware-friendly. The accelerator we designed is shown in Figure8:a, and consists of a WTA-circuitry for solving and enforcing the Sudoku constraints, congurable externally by sending spikes to the conduit (to set Sudoku clues), and updates the network one timestep per clock cycle. Each timestep, all 729 neuron spike outputs (if any) are latched into the checker network, which rejects invalid puzzles. In short, one component is searching for plausible solutions, and the other component rejects invalid solutions. The spike checker networks are negligible in area and are not on the critical path. 18 Synthesis of our accelerator is shown in Table4. On the FPGA, the accelerator is logic-bound, consuming 87% of device resources and 40% of all DSP resources, running at a peak clock frequency of 63 MHz. A hypothetical ASIC variant using the ASAP 7nm PDK and Cadence Genus estimations would consume order 2 million standard cells, be 177kμm 2 , and run at 208.2 MHz. Our accelerator performance, compared to the state-of-the-art optimization solvers CP-SAT, SCIP, and the handwritten tdokusolver (claimed to be the world’s fastest solver), is shown in Figure8:b on all 46 Vaasa puzzles [63]. The Vaasa puzzles are a combination of easy to hard puzzles, and include the notoriously hard AI escargot puzzle (s16). Results show that SCIP [30], CP-SAT [31], and tdoku [32] solve all 46 puzzles correctly in 173.2 ms, 142.5 ms, and 82.3μs, respectively, on a modern server machine. Our Syn2Logic FPGA accelerator solves all 46 puzzles correctly within 6.19 ms, and the hypothetical ASIC variant within 1.80 ms– many times faster than both SCIP and CP-SAT. While tdoku is still much faster than Syn2Logic, in fact, our accelerator solves several individual puzzles faster than tdoku, such as s01b, s06a, s06b, s06c, s10b, and s13b. It is not unlikely that for these puzzles, our accelerator is the fastest solver currently in the world. 3.4.1 Generalization to other puzzles Does our neuromorphic solver generalize outside the very same puzzles we tuned it for? Does it still perform well? To answer this, we rst tested it on a dierent but equally hard Sudoku testing set, the Euler-96. Our solver solves all 42 of these puzzles, consuming 2.79 ms/ 0.81 ms (FPGA/ASIC) for the whole set and between 0.51us/0.17usand 427.8 μs/ 124.1μs per-puzzle solution time. CP-SAT and SCIP solve the entire set in49.5±22.0ms and96.7±4.3ms, respectively, and our solver continues to be 17.74x/61x (FPGA/ASIC) and 34.65x/119x (FPGA/ASIC) faster than CP-SAT and SCIP, respectively. tdoku continues to be the fastest with a total time of 0.073 ms, which is 11x faster than our solver ASIC solver; our ASIC solver solves ve puzzles (out of 42) 1.16x-4x faster than tdoku. Fig. 9: Generalization testing our Sudoku solver on puzzles non-tuned for and in comparison with the software solvers. The ultimate test of generality is whether our solver can solve the top1465— a set of 1465 handpicked hard puzzles [ 64]; these puzzles are signicantly harder ( 5-35x based on the number of guesses needed) than our previous tests. Results are shown in Figure9. Our solver solvesall1465 puzzles in 3.94s/1.14s (FPGA/ASIC), dominated by a set of 15 puzzles that need>2 million steps to solve, with the main culprit (puzzle p0330) taking 10 million cycles to solve, and half the total time is spent on 50 (out of 1465) hardest puzzles. CP-SAT and SCIP both solve the entire puzzle in 5095.8±6.2ms and7516.1±153.1ms, respectively, reducing the speed-up our solver has over CP-SAT to 1.29x/4.47x (FPGA/ASIC) and SCIP to 1.9x/6.59x (FPGA/ASIC)— still a large improvement, but reduced compared to the simpler puzzle. tdoku continues to be blazing fast, with a total time solving all puzzles of12.275±0.008ms— a speedup of 320x/92x over our solver variants. Over tkodu, as we only solve four puzzles (out of the 1465) 1.07-1.83x faster than it. 19 3.4.2 Discussion: eNDA Enables High-Performance Practical SNN-based Optimizers Until now, prior neuromorphic accelerators and simulators had a per-puzzle solution time in order of seconds [65]; our work shows that we can employeNDAto create neuromorphic accelerators that have as low as sub-uspuzzle solver time and outperform state-of-the-art optimization solvers (CP-SAT/SCIP) by up to 28x on an FPGA and 96.2x if an ASIC were manufactured. We also show – for the rst time and for asmallsubset of puzzles – that a neuromorphic solvercan outperform the world’s fastest sudoku solver (tdoku) running on a state-of-the-art server-class system on some puzzles. We also showed that our solver generalizes, and solves harder puzzles than what it was tuned for, solving the entire top1465 puzzle list. Aside from theeNDA-ow, which is central to the success of the hardware accelerator, there are two very interesting observations:(i)our neuron model actually worked the best with a very large integration time step of over2ms, and(i)a small xed-point representation actually allowed (for this particular conguration) to solve more puzzles than its larger counterpart. Our work paves the way toward enabling neuromorphic optimization solvers to be a serious alternative to traditional solvers, and to be far more energy-ecient (ASIC estimates are61.3mW, which is 3-4 orders of magnitude lower than the server-class processor we compared against), making it suitable for serious exploration of real use-cases such as Edge-User Allocation [66] or scheduling sports events and/or airplanes. A nal note on the conguration of the puzzle: our experiments did not take into account either the binary loading overhead of the software solver. Our accelerator can load a puzzle instance in a single cycle, so likely – if we also include the time to recongure a new puzzle – the results would favor our accelerator even more. 3.5 Extreme Energy-Ecient MNIST Accelerator We end our results with a familiar use case: identifying handwritten digits using the MNIST dataset. While not the largest, the MNIST dataset still represents a cornerstone for evaluating — and more importantly, comparing — neuromorphic systems with each other. The dataset comprises 60000 training and 10000 test images of 28x28 pixels that are black and white, where each corresponds to the written value 0-9. Our goal was to create the most energy-ecient neuromorphic MNIST classier to date, runnable on hardware that is readily available and cheap (in contrast to the Agilex7 board in prior sections). Our goal was to use neuromorphic design automation to make a MNIST accelerator for a systemthat is nancially accessible to a broad audience, such as the MAX10 toy-FPGA, released in2014and built using a55nmtechnology. After training a 784-128-64-10 layer MLP network containing 110k parameters using snnTorch, we start our design- space exploration. The initial network demonstrated 97.61% testing accuracy, well in line with current state-of-the-art. Next, we will explore the design space of the network. We start with the impact of sparsity of the network, in Figure10:a. We noticed that the network can be pruned by 80-90% of existing parameters with minimal impact on classication accuracy, especially when coupled with ne-tuning of the network after pruning, yielding an accuracy of 97.23% and 95.06% test accuracy for 80% and 90% pruned networks, respectively. While this is a respectable amount of pruning, in fact, such a network is still far too large to t on the 50k look-up tables on the MAX10 board, due to the many adders that make up reduction trees per neuron. 20 Fig. 10: (a) Impact of weight-pruning on our network, (b) impact of our per-model bandwidth parameter on the pruned network, (c) impact of reducing the SNN data-path width on the network, and (d) impact of timesteps on the accuracy and per-model bandwidth. Next, we investigated the impact of per-model bandwidth reduction on the already sparse network, in Figure10:b. We noticed that we can reduce the per-model bandwidth between 80% and 90% without losing much test accuracy, again exploiting ne-tuning to reach between 97.24% (upper, interestingly 0.02% better test accuracy after ne-tuning than pmw=1.0/80% baseline) and 94.31% (lower) test accuracy. By reducing the per-model bandwidth, we eectively reduce the number of adders required in the reduction step per neuron, from 10919 (pmw=1.0) to 1883 (pmw=0.2) and 901 (pmw=0.1) Having sparsied and reduced the per-model bandwidth of the network, we next investigate the impact of data-path size on our network, in Figure10:c, by plotting and investigating the test accuracy as a function of data-type size. We noticed that we can reduce the size of operations to as low as 5 bits with small impacts on the accuracy, compared to ourQ 16:16 reference. This means that we can still achieve 93%+ accuracy with aQ 1:3 format. An interesting observation and experiment can be seen in Figure10:d, where we investigate the impact of per-model bandwidth as a function of how many timesteps we run the network and input for. An interesting observation is that, as the timestep increases from 25→50 timesteps, it becomes more resilient to degradations from a reduced bandwidth per model. This is intuitive, since longer timesteps can lead to more sparse activations in the network, which in turn lead to fewer spikes incoming to each neuron. The interesting part is that, by controlling the sparsity of the network, this impacts hardware generation signicantly, since at a 90+% reduction in per-model bandwidth together with the earlier sparsity pruning, most of the adder-trees are gone, and replaced with only the priority-encoders and multiplexers. 21 Table 5: FPGA and ASIC synthesis results for the MNIST accelerator. MAX10Agilex7ASAP7 Design point Weight sparsity / synapses90 % / 10,91980 % / 21,83780 % / 21,837 Per-model bandwidth (--pmw) 0.10.20.2 Datapath (--fixed-point)Q 1:3 (5 bits)Q 1:4 (6 bits)Q 1:4 (6 bits) TimestepsT(= cycles/image) 252525 Accuracy, full 10k test set93.80 %97.07 %97.07 % Implementation Logic38,103 LE (77 %)26,684 ALM (5 %)110,146 std cells of which the classier18,759 LEallall Registers12,498 (classier 1,074) 4,077— On-chip memory33,744 bits (92 M9K)— Cell area—8,765μm 2 die—21,764μm 2 Closure and cost Clock constraint43 MHz400 MHz500 MHz F max 45.28 MHz214.82 MHz (prelim.) 491 MHz Power307 mW—17.96 mW Latency per image581 ns116 ns51 ns Energy per image179 nJ—0.91 nJ Fig. 11: (a) the ASIC oorplan for the placed-and-routed chip (each neuron is clearly shown), and (b) just after the power measurement for the MAX10 device when inferring a hand-drawn number 5 (the observant reader will see the fth LED shining strongest, indicating a correct inference). At this time, we can start synthesizing our accelerators, with results shown in Table5. We created three dierent variants, suitable for MAX10, Agilex7, and ASIC ASAP7 generation. The MAX10 variant uses the 90% sparse network inQ 1:3 format with 90% (T=25) per-model bandwidth reduction and reaches 93.80% testing accuracy, consuming 77% of device resources and no DSPs. The MAX10 power consumption was empirically measured to be 0.307 Watt. For the larger Agilex7 system, we show results for a variant that uses the 80% sparse network withQ 1:4 format with 80% per-model bandwidth reduction and reaches 97.07% test accuracy, consuming a minimal fraction of the resources (5%). Finally, we show synthesis results for the ASAP7 accelerator that uses the same conguration as the Agilex7 variant, consumes 110k standard cells, and is estimated at17.96mWpower consumption. The ASIC oorplan is shown in Figure11:a. Performance-wise, the ASIC version is the fastest at 491 MHz, followed by the Agilex7 at 214 MHz and lastly the MAX10 at 45.28 MHz. An image of the MAX10 power-consumption measurement evaluation (or directly after, actually, with the snapshotted measurement still visible) inferring a hand-written number 5 is seen in Figure11:b. 22 Fig. 12: (a) Frame-per-second (FPS) performance of our Syn2Logic accelerator over state-of-the-art neuromorphic systems, and (b) FPS/Watt over state-of-the-art systems. Fig. 13: Energy-eciency versus classication accuracy for dierent MNIST accelerators. The performance (FPS) of the accelerators and their energy eciency (FPS/Watt) are shown in Figure12:a-b and are compared with the reported performance of state-of- the-art SNN accelerators inferring MNIST. Performance-wise, our Agilex7 and ASIC accelerators are up to 109-249x faster than DeepFire2, respectively, while the MAX10 version is 21x faster than the runner-up DeepFire2. From an energy-consumption perspective, the ASAP7 performance could be up to 1.11 GFPS/Watt, while the MAX10 measured energy consumption is 5.60 MFP- S/Watt— 1.5x more power-ecient than the IBM TrueNorth runner-up. Remaining SNN accelerators are 32.7 kFPS/Watt and below. Figure13we see a dierent view of the state-of-the-art landscape, where we plot power-eciency as a function of inference classication accuracy (%). We see that, for 23 the inference accuracy Syn2Logic acceler- ator provides, they are signicantly (many orders of magnitude) more energy-ecient than alternatives, even when compared to other accelerators that pro- vide the same (or less) inference accuracy. While there are several accelerators reaching a higher accuracy than our 97.07%, those 1-2% comes at a four orders of magnitude cost in battery drainage. We have to acknowledge that the ASAP7-variant is an estimation for the core only. Furthermore, these numbers assume that we can feed the images to the accelerator at the maximal FPS; while this is true for the MAX10-accelerator (that would hypothetically need to be fed with HBM2-quality external memory), there is nothing external that could feed 19.65 million images for the ASIC or 8.59 million images for the high-end FPGA, so these systems are more memory-bound than compute-bound. That being said, there are ample opportunities to tune these accelerators to the data source. For example, if the data source is an event-driven camera operating at 40 FPS, then the clock frequency can be signicantly reduced for the device to draw even less energy. There is also one dimension not thoroughly explored in our work: the number of timesteps per image. In our work, we used a conservative 25 timesteps per image, while most other work uses between 4 and 8, which linearly reduces the required data bandwidth to provide the data. In short, for a timestep of four, all our performance numbers would be 6.25x higher. 3.5.1 Discussion: eNDA for Extremely Energy-Ecient TinyML on FPGAs Our accelerator numbers could, to the best of our knowledge, be the most energy-ecient MNIST neuromorphic numbers in the world. Now, this might not be an apples-to-apples comparison, since every one of the reported accelerators used a dierent network architecture (SCNN, SMLP, etc.) with varying model parameter count (we used 110k, DeepFire2 139k, Sommer et al. 17k, etc.). With that being said, let the result sink in: we trained an S-MLP network in a matter of hours, explored the design space using Syn2Logic, and created a MNIST classier that reaches world-record 1.72 Million FPS with an eciency of 5.6 Million FPS/Watt (full System-on-Chip, not only estimations of the IP module), beatingall current top-end SNN accelerators on MNIST inference, runningon a toy FPGAthat is signicantly cheaper, older (2014), and more constrained than any of the competitionwithout writing a single line of hardware description language codeusing oureNDA-ow. 4 Conclusion In this paper, we have presented the rst complete NDA ow, allowing push-button end-to-end generation of neuromorphic systems. Furthermore, we have introduced Syn2Logic— an NDA prototype system implementing the entire NDA ow- and created a class-4 backend targeting the creation of digital neuromorphic systems. We evaluated our proposed NDA Flow and prototype implementation on a set of well-known neuron and synapse models— some, such as the BCPNN synapse, which is seen in hardware for the rst time— and nally proceeded to adopt our methodology to break three (to our knowledge) performance records:(i)World’s fastest simulation of theC. eleganslevel-A nematode model for computational neuroscience,(i)a Sudoku accelerator that (for the rst time ever) is capable of solving puzzles faster than generic optimization solvers (but does not yet reach tdoku-levels), generalizes to the TOP1465 puzzles set, and is many orders of magnitude faster than prior neuromorphic solvers, and(i)world’s most energy ecient spike-based MNIST accelerator, reaching 5.6 million frames-per-second per Watt spent on a 12-year-old toy-FPGA, with ASIC estimates at >1 billion frames-per-second per Watt. A word on AI: An interesting experience is also in the use of generative AI for transporting models between dierent neural descriptions. One problem in neuroscience is a common language for describing neural networks (Brian2, NestML, NeuronML, SpineML, Syn2Logic, all use dierent grammars). We found that using generative AI worked remarkably well to move between dierent languages, as long as proper validation suites were present (e.g., generating traces using Brian2, moving the model to Syn2Logic using generative AI, and then verifying using traces). So in the future, perhaps generative AI will be the component that unies cross-framework development between these modelling frameworks. Limitations and Future Work: Future work should cover some of the limitations of the backend. Our backend lays out all neuromorphic components directlyin silico, which is well within the spirit of digital implementations of traditionally analog neuromorphic systems [57]; our backend — while being extremely performant— cannot easily handle a large number of neurons/synapses before running out of silicon real estate (order10 3 neurons on mid-tier FPGAs, possible reaching10 4 neurons on high-end FPGAs)– not entirely unlike their analog counterparts. We see three directions. The rst direction could thus be to extend the class4 backend to operate not only in 2D, but also towards 3D monolithic integrated circuits, which could provide more capacity and synergize well with the sparse, biologically plausible nature of spiking neural networks that could assist in the troublesome thermal gradients in such systems. A second direction would be to create a backend that temporally shares the data paths across states, which is in line with most prior digital neuromorphic systems; such a backend would have signicantly more capacity, limited only by the amount of external (or on-chip) RAM resources, but would also be slower and less deterministic, and could lose some of the edge that the current backend provides. A third, and maybe most radical, direction is to create a backend that 24 maps the ODEs and model/network structures to an (possibly mixed-signal) analog/memristive technology, allowing exploration of future post-Moore substrates from the NDA ow without changing the descriptions. 5 Methods 5.1 Syn2Logic Implementation The Syn2Logic compiler consists of 17500 lines of C/C++ code that was written manually by the author. The lexical analysis is performed using FLEX, and we created a hand-written recursive-descent parser. Together, these are 2600 lines of program code, and the remaining program code is for the intermediate optimizations and backend generation. 5.2 Fixed-Point Representation All Syn2Logic generated code used a xed-point representation, represented by two integersMandNin the form QM:N, whereMare the number of integer bits andNthe number of fractional bits, giving a total word length of M N1bits, a representable range of±2 M and a quantisation step of2 −N . 5.3 Neuron Models Exploration 5.3.1 Leaky Integrate-and-Fire (LIF) The LIF neuron integrates its membrane potentialVaccording to the linear subthreshold dynamics C m dV dt =g L E L −V I,g L = C m τ m ,(1) and emits a spike whenVcrosses a xed thresholdV th , after whichVis reset instantaneously toV reset . The parameters are a membrane capacitanceC m =250 pF, a membrane time constantτ m =10 ms(so thatg L =C m τ m =25 nS), a leak and resting potentialE L =−70 mV, a thresholdV th =−55 mV, and a resetV reset =−70 mV. Brian2 integrates this equation analytically (exact integration) and Syn2Logic usesLIFwith a membrane resistanceR mem =τ m C m =40 MΩ, which reproduces the reference leak conductance, retaining the library-default threshold and reset of−55 mVand −70 mV. 5.3.2 Izhikevich The Izhikevich neuron is a dimensionless two-variable model coupling a membrane-like variablevto a recovery variableu, dv dt =0.04v 2 5v140−u I,(2) du dt =a b v−u,(3) with the spike-and-reset rule ifv≥30 mV :v←c, u←u d.(4) Here the injected currentIis the model’s native dimensionless drive rather than a physical current in picoamperes. We use the canonical regular-spiking parametersa=0.02,b=0.2,c=−65 mV, andd=8, with a peak/cut-o of 30 mV. Brian2 integrates with forward Euler and initialisesv0=c,u0=b cand Syn2Logic usesIzhikevichwith the matching library-default coecients. 5.3.3 Adaptive exponential integrate-and-re (AdEx) The AdEx neuron augments an exponential spike-initiation term with a slow adaptation currentw, C m dV dt =g L E L −V g L Δ T exp ( V−V T Δ T ) −w I,(5) τ w dw dt =a V−E L −w,(6) with the reset, applied whenVexceeds the cut-oV peak , ifV > V peak :V←V reset , w←w b.(7) 25 The parameters areC m =281 pF,g L =30 nS,E L =−70.6 mV, an exponential onset thresholdV T =−50.4 mV, a slope factorΔ T =2 mV, a subthreshold adaptation conductancea=4 nS, an adaptation time constantτ w =144 ms, a spike-triggered adaptation incrementb=80.5 pA, a resetV reset =−60 mV, and a spike cut-oV peak =0 mV. Brian2 integrates with forward Euler fromw0=0and Syn2Logic usesAdEXwith the matching library defaults. The Syn2Logic model emits a spike whenVcrossesV T ; because the exponential term diverges within a single step once V > V T , this is numerically equivalent to theV peak =0cut-o used by the references. 5.3.4 Hodgkin-Huxley Model The classic conductance-based H neuron resolves the action potential explicitly through voltage-gated sodium and potassium channels, C m dV dt =I−g Na m 3 h V−E Na −g K n 4 V−E K −g L V−E L ,(8) where each gating variablex∈m, h, nrelaxes according to dx dt =α x V1−x−β x V x,(9) with the standard textbook rate functions (voltageVin millivolts, rates inms −1 , resting potential≈−65 mV) α m V= 0.1V40 1−e −V4010 ,β m V=4e −V6518 ,(10) α h V=0.07e −V6520 ,β h V= 1 1e −V3510 ,(11) α n V= 0.01V55 1−e −V5510 ,β n V=0.125e −V6580 .(12) The parameters areC m =100 pF, a maximum sodium conductanceg Na =12 000 nS(12μS), a maximum potassium conductanceg K =3600 nS(3.6μS), a leak conductanceg L =30 nS, and reversal potentialsE Na =50 mV, E K =−77 mV, andE L =−54.402 mV. Brian2 integrates with the exponential-Euler method from the resting steady state (m=0.0529,n=0.3177,h=0.5961) and Syn2Logic usesHHwith the matching library defaults, detecting a spike on the upward zero-crossing ofVvia a re-arming threshold ag that guarantees one count per action potential. 5.3.5 Numerical Integration The LIF, Izhikevich, and AdEx models are integrated atΔt=0.1 mson all Brian2 and Syn2Logic platforms. The H model uses0.01 msfor both frameworks. 5.3.6 Syn2Logic conguration For the initial correctness evaluation, Syn2Logic was invoked to generate hardware with a xed-point representation of Q32:24. Fused operations were enabled, and constant rounding was disabled. 5.3.7 Stimulation Protocol The injected current is swept over0to600 pAfor the LIF model,0to15(dimensionless) for the Izhikevich model,0to 900 pAfor the AdEx model, and0to1000 pAfor the H model. The software references sample these ranges densely (a current step of5 pA, or0.1for the dimensionless Izhikevich drive), whereas the Syn2Logic sweeps use a coarser step (20 pA, or0.5for Izhikevich) because each Syn2Logic point is a full compile-and-simulate cycle (using QuestaSim). 5.3.8 Precision sensitivity analysis. Fidelity between implementations quantied with the root-mean-square error between the two curves (test and reference), normalized by the dynamic range (swing) of the reference to make the metric dimensionless and comparable across models with widely dierent ring-rate scales: NRMSE=100× √ 1 N N i=1 ( f S2L i −f ref i ) 2 max i f ref i −min i f ref i %,(13) 26 wheref ref i andf S2L i are the reference and Syn2Logic ring rates at thei-th ofNcurrent points (points at which either curve is undened are excluded). NRMSE is reported as a percentage of the reference swing, and a conguration is deemedfaithfulwhen it meets a5%design budget. 5.4 Synapse Models 5.4.1 Plasticity models. Four canonical learning rules spanning the principal families of synaptic plasticity were studied:(i)pair-based spike-timing-dependent plasticity (PairSTDP),(i)triplet STDP, which augments the pair rule with a second-order postsynaptic trace;(i)a reward-modulated (“three-factor”) STDP rule (RSTDP) after Izhikevich[67], in which pre/post coincidences accumulate a decaying synaptic eligibility trace that is converted into a weight change only upon delivery of a global reward signal; and(iv)the Bayesian Condence Propagation Neural Network (BCPNN) synapse after Lansner and Tullyet al.[68] 7 . The synaptic weight was initialised tow0=0.5(dimensionless) in the three STDP-family rules. 5.4.2 Pair-based STDP. Two exponentially decaying eligibility traces,x pre andx post , record recent pre- and postsynaptic activity, dx pre dt =− x pre τ , dx post dt =− x post τ − ,(14) with the spike-triggered updates pre-spike:x pre ←x pre 1,w←w−A − x post ,g out ←g scale w,(15) post-spike:x post ←x post 1,w←w A x pre .(16) Parameters:τ=τ − =20ms,A=A − =0.01, output scaleg scale =5. 5.4.3 Triplet STDP. The triplet rule [ 69] adds slow pre- and postsynaptic tracesr 2 , o 2 to the fast pair tracesr 1 , o 1 , dr 1 dt =− r 1 τ , dr 2 dt =− r 2 τ x , do 1 dt =− o 1 τ − , do 2 dt =− o 2 τ y ,(17) with the triplet-modulated updates pre-spike:w←w−o 1 A − 2 A − 3 r 2 ,r 1 ←r 1 1, r 2 ←r 2 1,(18) post-spike:w←w r 1 A 2 A 3 o 2 ,o 1 ←o 1 1, o 2 ←o 2 1,(19) andg out =g scale wemitted on each pre-spike. Parameters: fast decaysτ=16.8ms,τ − =33.7ms; slow decays τ x =101ms,τ y =125ms; pair amplitudesA 2 =0,A − 2 =0.0072; triplet amplitudesA 3 =0.0062,A − 3 =0; g scale =1. The second-order traceo 2 sets this rule’s integer-bit requirement. 5.4.4 Reward-modulated STDP. RSTDP [ 67] is a three-factor rule: the same pre/post traces feed a slowly decaying eligibility tracee, dx pre dt =− x pre τ , dx post dt =− x post τ − , de dt =− e τ e ,(20) with pre-spike:x pre ←x pre 1,e←e−A − x post ,g out ←g scale w,(21) post-spike:x post ←x post 1,e←e A x pre ,(22) so that spike timing only builds eligibility; a separate reward event converts it into a weight change, reward:w←w R e,(23) 7 Reference Brian2 code given by Anders Lansner, Pawel Herman, and Ferdinand Bujanowski. 27 and the reward does not resete. Parameters:τ=τ − =20ms, eligibility decayτ e =1000ms,A=A − =0.01, reward magnitudeR=1.0,g scale =1. All internal signals stay below unity, but the updatew=R eis a product of two small quantised quantities. 5.4.5 BCPNN. The BCPNN synapse [70] in which low-pass-ltered spike (Z), eligibility (E) and probability (P) traces estimate pre-, post- and joint ring probabilities, and the synaptic weight is the log-odds w=log P ij P i P j .(24) Each input spike sets a one-timestep pulsespk i that decays with the spike duration,dspk i dt=−spk i t spike (and likewisespk j ), driving the spike (Z), eligibility (E) and probability (P) traces dZ i dt = spk i f max t spike −Z i ε τ z , dZ j dt = spk j f max t spike −Z j ε τ z ,(25) dE i dt = Z i −E i τ e , dE j dt = Z j −E j τ e , dE ij dt = Z i Z j −E ij τ e ,(26) dP i dt = E i −P i τ p , dP j dt = E j −P j τ p , dP ij dt = E ij −P ij τ p ,(27) The drive term1f max t spike =500is the largest internal quantity in any of the four rules and sets this synapse’s integer-bit oor. Parameters:f max =20Hz, oorε=0.05,t spike =0.1ms,τ z =10ms,τ e =100ms,τ p =1000ms; marginal traces initialised toεand joint traces toε 2 . 5.4.6 Induction protocols. Each rule was driven by a deterministic spike protocol designed to exercise its characteristic dynamics. PairSTDP and TripletSTDP received a mixed pairing protocol combining potentiating and depressing pre/post orderings across repeated bursts (3,680timesteps,Δt=1ms). RSTDP received a four-phase protocol (causal pairing with reward; causal pairing without reward; anti-causal pairing with reward; causal pairing followed by a delayed reward), with a quiescent washout longer than twice the eligibility time constant between phases so that each phase began from a null eligibility trace. BCPNN received the ve-section correlation protocol of Tullyet al.(correlated, independent, anti-correlated, silent, and postsynaptically-muted epochs;10s total,Δt=0.1ms, peak rate20Hz), with spike trains drawn from a seeded pseudo-random generator so that hardware and reference implementations received bit-identical input. Protocols consisting only of binary spike events are independent of the xed-point format and were generated once; the RSTDP protocol additionally carries an analogue reward payload whose port width scales as QM:N, and was therefore regenerated for every format. 5.4.7 Cycle-accurate simulation. Each compiled model was co-generated with a self-checking VHDL testbench that applies the protocol one row per clock cycle (one clock cycle corresponds to one biological timestep) and records every state variable each cycle. Testbenches were compiled and simulated cycle-accurately in a QuestaSim. 5.4.8 Precision sensitivity analysis. For every rule we recorded the full weight trajectorywtat each xed-point format and quantied its delity relative to a high-precision reference format (16:16for the STDP-family and RSTDP rules;24:24for BCPNN). Fidelity was expressed as the normalised root-mean-square error ofwtagainst the referencew ref t, NRMSE= √ 1 |T| t∈T ( wt−w ref t ) 2 max t w ref t−min t w ref t ×100%,(28) normalised by the reference weight swing and reported as a percentage. The setTcomprises only those cycles at which both trajectories are nite, guarding against xed-point underow of the BCPNNP-traces (for which the log-odds in Eq.(24)are undened). TheM, Nplane was rst mapped at coarse resolution to locate the operating region and subsequently at single-bit resolution over the relevant range to resolve ne structure. From each map we extracted, for a xed error budget (5%NRMSE), the smallest total word lengthM N1achieving that budget, and the minimum integer width below which the largest internal trace of each rule saturates. 28 5.4.9 Reference validation and reproducibility. The BCPNN hardware synapse was cross-validated against an independent Brian2 implementation of the same equations driven by the identical seeded protocol. All protocols are deterministic and all simulations reproducible from the provided generators, compiler ags (--fixed-point=M:N,--timestep,--testbench) and simulation scripts; the per-format state traces and the derived NRMSE maps are archived as machine-readable CSV. 5.5 Caenorhabditis elegans Reference network. We evaluate our neuromorphic compilation ow on theC. elegansconnectome, using thec302Level Amodel as the ground-truth specication. The network comprises 302 neurons with the full set of chemical and electrical (gap- junction) connections dened byc302. All neurons are integrate-and-re cells driven by a uniform tonic input of 2.1 pAwith a at gap-junction conductance, the operating point at which the model produces stable, non-degenerate activity across the whole network. It is transcribed into the Syn2Logic domain-specic language as a single at network, preserving the per-synapse weights and neuron parameters of the NeuroML description. Software baselines. To establish a reference spike train we simulate the same network with three independent simulators: jNeuroML (the LEMS reference interpreter), Brian2, and NEST (32 OpenMP threads). All three integrate for1000 msat a xed time step of0.1 ms(10k steps). Hardware compilation. Syn2Logic compiles the.s2ldescription directly to synthesizable VHDL. The generated datapath advances the entire network by one simulation time step every clock cycle, so the1000 msexperiment maps to exactly 10 000 clock cycles independent of ring activity. Two orthogonal knobs reduce hardware cost while preserving accuracy:(i)a xed-point number format, here Q7:15 (7 integer, 15 fractional bits) with non-fused arithmetic; and(i)a synapse-pruning factorpmw, set to0.2, which only propagates the 20 % active synaptic weights into the neurons. Constant coecients are additionally quantised with up to1 %relative error (--round-constants=0.01). We verify the emitted RTL bit-exactly against the compiler’s xed-point model in Siemens QuestaSim, using a testbench that counts per-neuron spike events; the resulting spike train reproduces the software baselines with a correlation of0.9967(windowed 200–1000 mserror of0.94 %against the full-precision32:32reference). Physical implementation. The same VHDL is pushed through two independent compiler-generated back-end ows. For the FPGA target we use Intel Quartus Prime Pro on an Agilex 7 device (AGFB014R24B2E2V); for the ASIC target, the Cadence ow (Genus synthesis and Innovus place-and-route) with the ASAP77 nmpredictive standard-cell library at the typical corner (0.7 V,25 ◦ C). Both ows emit an identicalout.vhdl(matching MD5 checksums), so the two results describe the same numerical model. Frequency, area, and power are read from the vendor reports; the maximum operating frequency isf max =1T clk −WNSfrom the worst negative slack of the setup-critical path. 5.6 Sudoku Accelerator 5.6.1 Puzzles used and Performance Measurements Tuning our SNN accelerator was performed on all 46 puzzles proposed by Mantere–Koljonen [63]. Generalization was tested using the TOP1465 [64] and Euler 96 [71]. We removed the overlapping puzzles between Mantere-Koljonen and Euler 96. For performance testing, we only counted time to solve the puzzle and not application binary/hardware startup time or puzzle conguration (including the setup time would skew the results signicantly in favor of the single-cycle neuromorphic conguration). For CP-SAT, we tested the strong scalability on the puzzles and used the single worker version, which was the fastest. 5.6.2 Solvers used We compared our neuromorphic solvers to three other state-of-the-art methods. SCIP (Solving Constraint Integer Programs) is a widely used open-source solver for mixed-integer programming (MIP) and mixed-integer nonlinear programming (MINLP), developed primarily at the Zuse Institute Berlin. It combines branch-and-bound, cutting planes, and constraint programming in a plugin-based framework that lets users customize components like branching rules, heuristics, and constraint handlers. 29 CP-SAT is Google’s open-source constraint programming solver, distributed as part of the OR-Tools suite. It reformulates integer and combinatorial problems as boolean satisability (SAT) problems and solves them using a clause-learning SAT engine combined with linear programming relaxations, constraint propagation, and large neighborhood search, running multiple strategies in parallel. Tdoku is a highly optimized open-source Sudoku solver written in C++ by Tom Dillon, designed to be among the fastest in existence for both easy and hard puzzles. It models Sudoku as a constraint satisfaction problem using a compact box-band representation and applies vectorized with SIMD instructions (SSE/AVX2/AVX-512) for speed. 5.6.3 Sudoku Neuron model Each of the9×9×9=729neuronsB x,y,z (cellx, yasserting digitz1) is an Izhikevich unit augmented with two per-neuron, exponentially decayingescape currentsthat let the winner-take-all (WTA) network leave local minima.v is the membrane variable andufor the recovery variable, afreeneuron (clue=0) updates as (please note how we compute0.04∗v∗vand not0.04∗v 2 to prevent product blow-up): v=0.04∗v∗v5v140−u ( I const −I syn −θ−r ) ,(29) u=a b v−u,(30) θ=−θτ θ ,r=−rτ r ,I syn =−I syn τ s .(31) θis the reverse adaptation current, andris a slower reverse current– both use as an annealer within the neuron. InhibitionI syn enforces the four Sudoku constraints: whenever a conicting neuron res,I syn ←I syn w syn n c , wheren c (described in Syn2Logic using the::numreducer) is the number ofsimultaneouslyconicting spikes (row, column, box, and one-digit-per-cell). A spike is emitted whenv≥v th =32, upon which v←c=−65,u←u d,θ←θΔθ,(32) followed by the oorv←maxv, cthat prevents the0.04v 2 positive-feedback well from re-diverging under strong inhibition. Aclue(given) neuron is pinned: it is driven byv=0.04v 2 5v140−u I set and is immune toI syn ,θ, andr. The system is integrated by forward Euler with stepΔt(also a tunable parameter). 5.6.4 Parameter search Finding parameters was key to a good Sudoku solver, and consumed nearly a week of overnight (iterative) searches. The dynamics are governed by several tunable parameters,Θ =a, b, d,Δt, I const , I set , w syn , τ s ,Δθ, τ θ , R amp , τ r . We optimise the single xed set that solves the largest number of the 46 Mantere–Koljonen benchmark puzzles [63] under a per-puzzle step cap, breaking ties by minimum total step count. Two properties of the landscape dictate the method. First, becausevevolves in single-precision oating point through a quadratic map, the good operating points arerazor-thin, isolated spikes(oating-point chaos), not smooth basins: gradient- or edge-pushing searches, and hill-climbing from a known-good point, repeatedly fail—nudging a single parameter o a winning value collapses the score. Second, evaluation is cheap and embarrassingly parallel. We therefore search byrandomised (Latin-hypercube- style) sampling over all twelve parameters at once, rather than rening locally, and validate any directional hypothesis with a cheap single-axis anchor probe before committing a sweep. The harness compiles the reference solver into an environment-tunable binary, evaluates all 46 puzzles per conguration, and tags every result line with its full parameter vector; runs are resumable and use fail-fast pruning (a conguration is abandoned as soon as it can no longer beat the incumbent). Over5.5∗10 4 congurations, this yields a single set solving all 46 with no per-puzzle retuning. Deploying on hardware is a second stage: the xed-point datapath (Q8:2) is adierentdynamical system, so the operating point is re-optimisedin the same way at the target precision rather than merely quantised from the oating-point solution. 5.7 S-MLP Accelerator 5.7.1 Training Our MNIST accelerator implements a fully connected spiking multilayer perceptron784−128−64−10(109 184 parameters, no biases). Neurons are non-leaky integrate-and-re (β=1, threshold1, reset-by-subtraction). Inputs are rate-coded: each pixel intensity is the Bernoulli ring probability of its input neuron, redrawn every timestep, and the class decision is the output neuron with the most spikes overT(25 or 50) timesteps. The network was trained using snnTorch [36] with backpropagation through time and a fast-sigmoid surrogate gradient on the standard MNIST split [72]. Hardware constraints are applied during training rather than after it: the network is rst pruned by weight magnitude and ne-tuned for ve epochs at a xed mask, and the per-neuron bandwidth limit is then ne-tuned for a further four epochswith the hardware selection in the loop, so the trained weights are the ones the 30 generated logic actually uses. All accuracies are the full10 000-image test set; repeated evaluation of one checkpoint varies by±0.3points with the Poisson seed. 5.7.2 Power Measurement and Estimation FPGA power is measured on the DE10-Lite (MAX10) board using a Siglent SDM4055A multimeter for the full System-on-Chip, which includes (except the Syn2Logic-generated accelerator) a JTAG interface, a JTAG command FSM, a Phase Locked Loop (PLL), and a spike buer holding one frame worth of data. A0.01 Ωsense resistor (R22) in the1.2 Vcore rail of the MAX10 device drops2.561 mVwhile the accelerator classies, giving256.1 mA and0.307 W. This is the whole system-on-chip on that rail, including the static leakage of the entire device, and is therefore an upper bound on the classier alone. For ASIC, we estimated the power using Cadence Voltus for the entire place-and-routed netlist at0.7 Vwith a500 MHzclock. 5.7.3 State-of-the-Art We compared against the following works: DeepFire2 [48], Sommer et al. [73], SyncNN [74], E3NE [75], SeaSNN [76], Fang et al. [77], FPGA-NHAP [78], Ju et al. [79], Spiker+ [50],Firey v2 [80], and Minitaur [81] on FPGA, and against TrueNorth [82], Loihi [21], and SpiNNaker [83] on ASIC. We used performance numbers taken from the paper itself and derived metrics only where possible (e.g., throughput and energy reported separately). The results spans work achieving between92 %and99.6 %MNIST accuracy on networks sized17k to647k parameters. 5.8 Software 5.8.1 NEST NEST (Neural Simulation Tool) is an open-source simulator for spiking neural network models, designed to study the dynamics, size, and structure of neural systems rather than the detailed morphology of individual neurons. It represents neurons as point or few-compartment models and focuses on the network level, making it well-suited for large-scale simulations involving thousands to millions of neurons and their connections. NEST is optimized for performance and scales eciently from laptops to high-performance supercomputers through parallel computing (using both threading and MPI). Models are typically built and controlled through PyNEST, its Python interface, while the computationally intensive simulation runs in a fast C++ core. It supports a wide range of neuron and synapse models, including plasticity mechanisms like STDP, and is widely used in computational neuroscience research. In our experiments, we used NEST 3.10. 5.8.2 Brian2 Brian2 is an open-source simulator for spiking neural networks, written in Python and designed around exibility and ease of model specication. Neuron and synapse models are dened directly as systems of dierential equations using standard mathematical notation and physical units, allowing custom dynamics, threshold and reset conditions, refractoriness, and synaptic plasticity rules to be expressed without low-level programming. To maintain performance despite this high-level interface, Brian2 uses runtime code generation: model descriptions written in Python are translated into ecient compiled C++ code that is executed at simulation time. The simulator provides a range of numerical integration methods, from exact integration for linear systems to numerical schemes for arbitrary equations, and supports monitoring of spikes, state variables, and population activity. We used Brian2 v2.10.1 in all our experiments. 5.8.3 Cadence EDA toolchain The digital implementation ow was carried out using the Cadence toolchain. Logic synthesis was performed with Cadence Genus v25.10, which takes the RTL description together with timing constraints (SDC) and a standard-cell library and produces an optimized gate-level netlist, performing logic mapping and optimization for timing, area, and power. The resulting netlist was then passed to Cadence Innovus v25.10 for physical implementation (place-and-route), where it is combined with the standard-cell library and physical (LEF) data to generate the nal routed layout. The Innovus ow encompassed oorplanning, power planning, placement (via the GigaPlace engine), clock tree synthesis (CCOpt), signal routing (NanoRoute), and concurrent timing and power optimization, yielding a placed-and-routed design from which area, timing, and power metrics were extracted. 5.8.4 Siemens Questasim QuestaSim is a commercial hardware simulator from Siemens EDA (formerly Mentor Graphics) used to verify digital designs written in VHDL, Verilog, or SystemVerilog before they reach silicon or an FPGA. 31 5.8.5 snnTorch The S-MLP architecture was implemented and trained using snnTorch v0.9.4, which is an open-source Python library that extends the PyTorch framework to spiking neuron models. snnTorch exposes spiking neurons, input encoders, surrogate gradients, and loss functions as native PyTorch modules, allowing SNNs to be constructed and trained using standard deep learning practices and inheriting PyTorch’s automatic dierentiation and GPU acceleration. Networks are dened by composing spiking neuron layers (such as leaky integrate-and-re units) with conventional PyTorch layers, and unrolled over discrete time steps to process temporally encoded inputs. 5.8.6 Altera Quartus Altera Quartus is a software toolchain used to design digital circuits for Altera FPGAs and CPLDs. Quartus lets a developer compile their designs, perform timing analysis, examine RTL diagrams, simulate the design’s reaction to dierent stimuli, and congure the target device with the programmer. Quartus Pro 26.1 was used for the Terasic DE10-Agilex platform, while Quartus Lite 18.1 was used for the DE10-Lite MAX10 board. 5.9 Experimental Platform All experiments were carried out on a server featuring two Intel Xeon Silver 4514Y, a total of 32 cores (64 hyperthreads) and 256 GB of DDR5 RAM. The system is running Rocky 9.8 with kernel 5.14.0-687.10.1. All performance-sensitive experiments on the server were executed in isolation using Slurm 25.11.4. For FPGA execution, we used a mid-range Terasic DE10-Agilex featuring an AGFB014R24B2E2V (1.4M LEs, 139 Mb SRAM, 4510 DSPs), as well as a low-range Terasic DE10-Lite featuring a MAX10 10M50 device (50k LEs, 1.6 Mb SRAM, 64 equivalent DSP blocks). Supplementary information.All data, scripts, results, Syn2Logic descriptions, VHDL les, FPGA bitstreams, language grammar, and the compiler itself will soon be made available as a independent docker image. Acknowledgements.This work was supported by the Swedish Research Council’s Project Building Digital Brains under Grant 2021-04579. The author would also like to thank Muhammad Ihsan Al Haz, Wiktor Jan Szczerek, Björn Lindqvist, Pedro Antunes, Pawel Herman, and Anders Lansner for valuable and interesting discussions on the neuromorphic topic over the years. Declarations TheSyn2Logic prototype framework has been – from start to nish – written by hand by the author, as has the description of all neural models. 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